JPS6336430A - Data processor - Google Patents

Abstract

PURPOSE:To reduce the hardware quantity and firmware quantity of a controller by inhibiting a leading-zero counting means from counting a leading-zero state when the output signal of a zero register indicates that a word which is high in order than a word inputted to a zero check circuit is not in an all-zero state. CONSTITUTION:The titled processor is provided with an inhibiting means consisting of a data converting circuit 13, etc., which inhibits the leading-zero counting means composed of a leading-zero detecting circuit 8, a leading-zero register 9, an adder, a zero count register 11, etc., from counting the leading-zero state when the output signal of the zero register indicates that the word is not in the all-zero state. The controller needs not decide whether the word higher in order than a word whose leading-zero state is counted is in the all-zero state or not, so the hardware quantity and firmware quantity of the controller are reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that performs leading zero counting of numerical data consisting of a plurality of words.

[Conventional technology]

When performing various calculations using numerical data consisting of multiple words, the calculation speed can be improved by removing consecutive zeros from the most significant digits and performing calculations using the numerical data from which these zeros have been removed. etc., it becomes possible to improve. In this case, it is necessary to know how many consecutive zero digits there are from the high-order digit, and conventionally, for example, the number of consecutive zero digits from the high-order digit is calculated as follows. ing.

FIG. 5 is a block diagram of a conventional example, in which 1 is a control device that controls each part by a microprogram, 2 and 3 are 1. The second register files 4, 5 are respectively the first . The second address register 6 checks whether the decimal character data read in word units from the register file 2 is all zeros. If all zeros, the output signal is set to 11"; if not, the A zero check circuit sets the output signal to "0", 7 is a zero register where the output signal of the zero check circuit 6 is set, and 8 is a zero register that sets the output signal of the zero check circuit 6 to "0". 0
9 is a leading zero register in which the detection result of the leading zero detection circuit 8 is set, 10 is an adder, and 11 is a zero count register. be.

Now, for example, 3 from address O of the first register file 2.
The 4-word numerical data stored up to the address is transferred to the second register file 3, and
Let us consider the case where leading zero count is performed on numerical data of this 4-word structure. FIG. 6 is a flowchart showing an example of the processing contents of the control device 1 at this time.

Incidentally, each of the processes in steps 361 to 368 in FIG. 6 is performed in one clock period.

First, the control device 1 sets “0” to the address register 4.5.
At the same time as setting the address, a reset signal a is applied to the zero count register 11, and the content ZCR of the zero count register 11 is set to "0" (step 561). As a result, the most significant word stored at address "0" in the first register file 2 is read out, and the most significant word stored in the "0" address of the first register file 2 is read out, and the most significant word is read out from the second register file 3. It is added to the zero check circuit 6 and the leading zero detection circuit 8. The zero check circuit 6 checks whether the characters included in the most significant word read from the register file 2 are all zeros. If all zeros, the output signal is set to 11", and if not, the output signal is set to "11". O”.

Furthermore, the leading zero detection circuit 8 detects "0" from the most significant word read from the register file 2 until a character other than "0" appears from the most significant character.
” Count the number of characters (number of digits).

Next, the control device 1 sends a write signal r to the register file 3.
By adding , the most significant word stored at address "0" in register file 2 is transferred to "
0'' address, and by adding the cent signal e to the zero register 7, the check result of the zero check circuit 6 for the most significant word is set in the zero register 7, and by adding the cent signal d to the leading zero register 9. By setting the detection result of the leading zero detection circuit 8 for the most significant word in the leading zero register 9 and setting the address "1" in the address registers 4 and 5, the result is stored at the "1" address of the register file 2. Read the second word from the top (step 562
). 2 read from address “1” of register file 2
The th word is register file 3. In addition to the zero check circuit 6 and the leading zero detection circuit 8, the zero check circuit 6 and the leading zero detection circuit 8 perform the same operation as described above for the second word.

Next, the control device 1 sends a write signal f to the register file 3.
By adding , the second word stored at address "1" of register file 2 is stored at address "1" of register file 3, and addition signal C is added to adder 10,
By applying a set signal S to the zero count register 11, the contents LDZR of the leading zero register 9 (in this case, the leading zero count value for the most significant word) and the contents ZCR of the zero count register 11 (in this case "0") are changed. Addition result to zero count register 1
1, and by adding a set signal e to the zero register, the check result of the zero check circuit 6 for the second word is set to the zero register 7, and by adding a set signal d to the leading zero register 9, the second word is set. By setting the detection result of the leading zero detection circuit 8 for the word in the leading zero register 9 and writing the address "2" to the address registers 4 and 5, the third word stored at the address "2" in the register file 2 is set. (step 563).

Next, if "O" is set in the zero register in the process of step 362, that is, if the most significant word is not all zeros, the control device 1 proceeds to step S64. If "1" is set in the zero register 7 in the process of step 362, that is, if the most significant word is all zeros, the process of step 366 is performed.

In step 364, the third word stored at address "2" of register file 2 is stored at address "2" of register file 3, and address register 4.5
The process of setting address "3" is performed, and step 3
At step 65, the fourth word stored at address "3J" of register file 2 is stored at address "3" of register file 3. Also, at step 366, the register is stored at address "2" of register file 3. Processing to store the third word stored at address “2” of file 2, contents of leading zero register 9 LDZR
(in this case, the leading zero count value for the second word) and the contents of zero count register 11 ZC
R (in this case, the leading zero count value for the most significant word) is added by the adder 10, and the addition result (in this case, the leading zero count value up to the second word) is set in the zero count register 11. ,
A process of placing the check result of the zero check circuit 6 for the third word in the zero register 9, a process of placing the detection result of the leading zero detecting circuit 8 for the third word in the leading zero register 9, and a process of placing the result of the check of the zero check circuit 6 on the third word in the zero register 4.5. Processing to set address "3" is performed. Here, the reason why counting of leading zeros is not performed in step 364 is because if the most significant word is not all zeros, it is meaningless to count leading zeros for words lower than the most significant word. be.

Next, if "1" is set in the zero register 7 in the process of step S63, the control device 1 performs the process of step S67 if the second word is all zeros, and sets "1" in the zero register 7 in the process of step S63. If "0" is set, that is, if the second word is not all zeros, the process of step S65 is performed. Step 36
7, the process of storing the fourth word stored at address "3" of register file 2 at address "3" of register file 3, and the content L of leading zero register 9.
The adder 10 adds DZR (in this case, the leading zero count value for the third word) and the content ZCR of the zero count register 11 (in this case, the leading zero count value from the most significant word to the second word). Then, the addition result (in this case, the leading zero count value up to the third word) is stored in zero count register 1.
1, setting the check result of the zero check circuit 6 for the fourth word in the zero register 7, setting the detection result of the leading zero detection circuit 8 for the fourth word in the leading zero register 9. Processing is performed.

Next, if "1" is set in the zero register field in the process of step S66, that is, if the third word is all zeros, the control device 1 performs the process of step 868, and sets "0" in the zero register 7 in the process of step S66. '' is set, that is, if the third word is not all zeros, the process moves to another control step. In step 36B, the content LDZR of the leading zero register 9 (in this case, the leading zero count value for the fourth word) and the content ZCR of the zero count register 11 (in this case, the leading zero count value from the most significant word to the third word) The adder 10 adds the values (values), and the addition result (in this case, leading zeros up to the fourth word) is stored in the zero count register 11.

[Problem that the invention seeks to solve]

Conventionally, the leading zero count is performed as described above, but as can be seen from the flowchart in FIG. The control device 1 makes a determination based on the determination result.
Since the processing contents of the control device 1 are changed, a comparator or the like is required to determine whether or not all words higher than the word read from the register file 2 are all zeros. In addition, there is a problem in that the amount of firmware increases because the processing content must be changed based on the determination result.

The present invention solves the above-mentioned problems.
The purpose is to reduce the amount of hardware and firmware in the control device.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention provides a data processing device that performs leading zero counting of numerical data consisting of a plurality of words, in which the plurality of words constituting the numerical data are input sequentially from the upper word. , a zero check circuit that checks whether the characters included in the input word are all zeros and outputs a signal indicating the result; a zero register to which the input signal is set; and an output signal of the zero register. By performing an AND with the output signal of the zero check circuit, a signal indicating whether or not the characters included from the most significant word to the word checked by the zero check circuit are all zeros is sent to the zero register. a zero accumulation circuit that outputs; a leading zero count means that counts the number of zero digits from the most significant digit of an input word until a non-zero digit appears, and sequentially adds the number of digits for each word; If the output signal of the register indicates that the words higher than the word input to the zero check circuit are not all zeros, counting of leading zeros by the leading zero counting means is inhibited, and the output signal of the zero register is suppressing means for inputting the same word as the word input to the zero check circuit to the leading zero count means when the word higher than the word input to the zero check circuit indicates that the word is all zero; , a control means for sequentially adding a plurality of words constituting the numerical data to the zero check circuit one word at a time starting from the upper word, and controlling the cent timing of the input signal of the zero register and the operation timing of the leading zero counting means; It has been established.

[For production]

The output signal of the zero register, into which the AND of the output signal of the zero check circuit and its own output signal is input, indicates whether or not all words higher than the word input to the zero check circuit are all zeros. . If the output signal of the zero register is all zeros than the word input to the zero check circuit, the suppression means adds the same word as the word input to the zero check circuit to the leading zero count means, and outputs the zero register. If the output signal indicates that the words higher than the word input to the zero check circuit are not all zeros, the counting of leading zeros by the leading zero counting means is inhibited. The value will indicate the leading zero count value.

(Embodiment) FIG. 1 is a block diagram of an embodiment of the present invention, in which 1' is a control device that controls each part by a microprogram, and 7' is a block diagram of an embodiment of the present invention.
12 is a zero register, 12 is a zero accumulation circuit, and 13 is a data conversion circuit, and the same reference numerals as in FIG. 5 represent the same parts.

FIG. 2 is a circuit diagram showing an example of the configuration of the zero accumulation circuit 12, which includes an AND circuit 21 that takes the logical product of the output signal of the zero check circuit 6 and the output signal of the zero register 7', and the output signal from the control device 1'. The selector 22 selects the output signal of the AND circuit 21 when the signal g is "1", and selects "1" which is the initial value of the zero register 7' when the signal g is "0". The zero accumulation circuit 12 stores 1 in the zero register 7' once "0" is written in the zero register 7'.
The output signal of the zero check circuit 6 is held at "O" until it is initialized, regardless of the output signal of the zero check circuit 6.

FIG. 3 is a circuit diagram showing an example of the configuration of the data conversion circuit 13, which includes an inverter 31 that inverts the output signal of the zero register 7', the most significant bit of the word read from the register file 2, and the inverter 31 that inverts the output signal of the zero register 7'. and an OR circuit 32 that performs a logical sum with the output signal of the output signal. That is, in the data conversion circuit 13, the output signal of the zero register 7° is "1".
In the case of , the word read from the register file 2 is directly added to the leading 0 detection circuit 8, and when the output signal of the zero register 7° is "0'", the word read from the register file 2 is added as it is. Be sure to set the bit to “1”
This is added to the leading zero detection circuit 8.

Now, for example, from address 0 to 3 of the first register file 2
The 4-word numerical data stored up to the address is transferred to the second register file 3, and
Let us consider the case where leading zero count is performed on numerical data of this 4-word structure. FIG. 4 is a flowchart showing an example of the processing contents of the control device 1 at this time.6 Note that each of the processing in steps 81 to S6 in FIG. 4 is performed in one crotter period.

The control '4'B device 1° first registers the address register 4.5.
By setting the address "0" to "0", the most significant word stored in the "0" address of the register file 2 is read, and by adding the reset signal a to the zero count register 11, the content ZCR of the zero count register 11 is set to "
0'', the signal g is set to 1, and the zero register 7
By adding the set signal e to ゛, the zero register 7
” is set to the initial value “1” (step 31).The most significant word read from the register file 2 is sent to the register file 3, zero check circuit 6, and data conversion circuit
Added to 3.

The zero check circuit 6 checks whether or not the characters included in the most significant word read from the register file 2 are all zeros. If all zeros, the output signal is set to "■"; if not, the output signal is “
In addition, in the zero accumulation circuit 12 to which the output signal of the zero check circuit 6 is applied, in this case, the zero register 7° is set to "1".
The output signal of the zero check circuit 6 is directly applied to the zero register 7'. Furthermore, in this case, since "1" is set in the zero register 7°, the data conversion circuit 13 applies the most significant word successively outputted from the register file 2 to the leading zero detection circuit 8 as it is.

Furthermore, the leading zero detection circuit 8 is connected to the data conversion circuit 1.
For the most significant word added through 3, count the number of characters in rOJ from the most significant character until a non-zero character appears.

Next, the control bag W1' adds the write signal f to the register file 3, so that the most significant word read from the address '0' of the register file 2 is stored in the '0' address of the register file 3.
0'' address, and by adding the cent signal e to the zero register 7', the check result of the zero check circuit 6 for the most significant word is set in the zero register 7';
By applying the set signal d to the leading zero register 9, the detection result of the leading zero detection circuit 8 for the most significant word is set to the leading zero register 9, and by setting the address "1" to the address register 4.5, the register The second word stored at address "1" in file 2 is read (step 32). The second word read from register file 2 is applied to register file 3, zero check circuit 6 and data conversion circuit 13.

When the second word read from the register file 2 is added, the zero check circuit 6 checks whether the characters contained in the second word are all zeros.
If all zeros are present, the signal applied to the zero accumulation circuit 12 is “1”.
”, and if the signal is not all zero, the signal applied to the zero accumulation circuit 12 is set to “0”. Also, in the zero accumulation circuit 12 having the configuration shown in FIG. Only in the case of "1" (when both the most significant word and the second word are all zeros), the signal applied to the zero register 7' is set to "1". Also, the third
When the output signal of the zero register 7° is "1" (when the most significant word is all zeros), the data conversion circuit 13 having the configuration shown in the figure converts the second word read from the register file 2 directly to the leading zero. Detection circuit 8
In addition, if the output signal of zero register 7゛ is °0'' (
If the most significant word is not all zeros), the most significant bit of the second word read from the register file 2 is set to "1" and is added to the leading zero detection circuit 8. Leading zero detection circuit 8 detects leading zero in the output data of data conversion circuit 13 and adds the detection result to leading zero register 9.

Here, if the most significant word is not all zeros, the most significant bit of the second word read from the register file 2 is set to "1" for the following reason. In other words, if the most significant bits are not all zeros, it is meaningless to count leading zeros for the second word, so if the most significant word is not all zeros, the most significant bit of the second word is set to "1". This is to set the leading zero count value of the leading zero detection circuit 8 to "0".

Next, the control device 1° stores the second word read from address “1” of register file 2 at address “1” of register file 3 by applying a write signal f to register file 3, and stores the second word read out from address “1” of register file 3 into address “1” of register file 3. Add the addition signal C to 10,
By adding a cent signal to the zero count register 11, the contents of the leading zero count register 9 can be changed to LD.
ZR (in this case, the leading zero count value for the most significant word) and the contents of zero count register 11 Z
CR (in this case, "0") and set the addition result (in this case, the leading zero count value for the most significant word) in the zero count register 11, and by adding the set signal e to the zero register 7. The output signal of the zero accumulation circuit 12 is sent to the zero register 7°, and the leading zero count value for the second word is sent by adding the cent signal d to the leading zero register 9, and the address register 4.5 is set to ``2''. '' address, the third word stored at address ``2'' of register file 2 is read out (step 33). The third word read in step S3 is applied to the register file 3, zero check circuit 6 and data conversion circuit 13.

The zero check circuit 6 applies a signal indicating whether or not the characters included in the third word are all zeros to the zero accumulation circuit 12.
and the output signals of zero register 7° are both “1” (
Only when all carries included in the third word from the most significant word are all zeros), the signal added to the zero register 7' is set to 1''.In addition, the data conversion circuit 13 sets the output signal of the zero register 7' to 1''. In the case (when both the most significant word and the second word are all zeros), the third word read from the register file 2 is directly added to the leading zero detection circuit 8, and the zero register 7°
When the output signal of is “O” (1st.

If the second word contains a non-zero character, the most significant bit of the third word is set to “1” and added to the leading zero detection circuit 8, and the leading zero detection circuit 8 converts the data into the data conversion circuit 13. The leading zero of the output data is detected and the detection result is added to the leading zero register 9.

Next, the control device 1'' applies a write signal f to the register file 3, thereby writing the 3 data successively written from the address ``2'' of the register file 2 to the address ``2'' of the register file 3.
By storing the th word, and adding an addition signal C to the adder 10 and a set signal S to the zero count register 11, the result of addition of the content LDZR of the leading zero register 9 and the content ZCR of the zero count register 11 is set to zero. Set in count register 11 and zero register 7
By adding a set signal e to ', the zero accumulation circuit 12
By setting the output signal of 0 to zero register 7° and adding cent signal d to leading zero register 9, 3
The detection result of the leading zero detection circuit 8 for the th word is written to the leading zero register 9, and the 4th word is read from the register file 2 by writing the address "3" to the address registers 4 and 5 (
Step 34). Here, since the leading zero count value for the most significant word is stored in the zero count register 11, the contents of the zero count register 11 ZCI? and leading zero register 9
If the characters included in the most significant word are all zeros, the leading zero count value from the most significant word to the second word can be obtained by adding the content LDZR. Note that if the characters included in the most significant word are not all zeros, the detection result of the leading zero detection circuit 8 will be rOJ as described above, but the zero count register 11 will contain the leading zero count for the most significant word. The value will be retained.

Next, the control device 1'' stores the fourth word at address "3" of the register file 3 by applying a write signal r to the register file 3, adds an addition signal C to the adder 10, and writes the zero count register 11. By adding a set signal to LOZ, the contents of the leading zero register 9 can be changed.
I? and the contents of zero count register 11 ZCI? By setting the addition result to the zero count register 11 and adding the set signal e to the zero register 7', the output signal of the zero accumulation circuit 12 is set to the zero register 7°, and the set signal d is applied to the leading zero register 9. By adding, the detection result of the leading zero detection circuit 8 for the fourth word is set in the leading zero register 9 (step S5)'.Here, if the most significant word and the second word are all zeros, the register file Since the third word read from 2 is directly added to the leading zero detection circuit 8, by adding the content LDZR of the leading zero register 9 and the content ZCR of the zero count register 11 in step S5, The leading zero count value from the most significant word to the third word will be determined. Furthermore, if there is a word that is not all zeros in a word higher than the third word, the most significant bit of the third word will always be "1", and the detection result of the leading zero detection circuit 8 will be rOJ. Therefore, the leading zero count value set in the zero count register 11 is not changed.

Next, the control device 1' applies an addition signal C to the adder 10 and a set signal S to the zero count register 11, thereby zeroing out the addition result of the content LDZR of the leading zero register 9 and the content ZCR of the zero count register II. Set in count register 11 (step S6
). Here, if the words higher than the fourth word are all zeros, the fourth word is added as is to the leading zero detection circuit 8, so in step $6 the contents of the leading zero register 9 [, DZR and By adding the contents ZCR of the zero count register 11, the leading zero count values from the most significant word to the fourth word can be obtained. Also, 4
If there is a word that is not all zeros in a word higher than the 4th word, the most significant bit of the 4th word will always be "1", and the detection result of the leading zero detection circuit 8 will be "0". The leading zero count value set in the leading zero register 11 is not changed.

In this way, this embodiment converts the word read from the register file 2 so that if the word higher than the word whose leading zero is counted is not all zero, the count value of the leading zero detection circuit 8 becomes zero. Therefore, the control device 1 does not need to determine whether or not the words higher than the word whose leading zeros are being counted are all zeros, and therefore the processing content of the control device 1 is It can be made simpler and the amount of hardware can be reduced compared to the conventional example.

In the above-described embodiment, if the word higher than the word whose leading zeros are to be counted is not all zeros, the most significant bit of the word whose leading zeros are to be counted is set to 1'' in the data conversion circuit 13. Accordingly, the updating of the zero count register 11 to which the leading zero count value is set is stopped, but the present invention is not limited to this, and it is of course possible to stop the operation of the adder 10, for example. be.

Furthermore, although not explained in the above embodiment, if all characters included in the words from the most significant word to the least significant word constituting the numerical data are zero, the content of the zero register 7' is "1". Therefore, it is possible to easily determine whether the numerical data is all zero based on the contents of the zero register 7'. On the other hand, in the conventional example shown in Figure 5, even if the content of the zero register is "1", it cannot be said that the numerical data is all zeros, and the Since the leading zero count value set in the zero count register 11 must be compared with the length of the numerical data, there is a problem in that it becomes troublesome to determine whether the numerical data is all zeros.

〔Effect of the invention〕

As explained above, in the present invention, if the output signal of the zero register indicates that the word higher than the word added to the zero check circuit is all zeros, the word added to the zero check circuit is Add the same word to the leading zero detection circuit, and if it shows that it is not all zeros, the leading zero detection circuit 8. Leading zero register9. It is equipped with a suppressing means consisting of a data conversion circuit 13, etc., which suppresses counting of leading zeros by a leading zero counting means consisting of an adder, a zero count register 11, etc., and the control device is installed in a higher order than the word for counting leading zeros. Since it is no longer necessary to determine whether or not all words are zero, there is an advantage that the amount of hardware and firmware of the control device can be reduced compared to the conventional example.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the configuration of the zero accumulation circuit 12, FIG. 3 is a circuit diagram showing an example of the configuration of the data conversion circuit 13, and FIG. 4 is a control diagram. FIG. 5 is a block diagram of a conventional example, and FIG. 6 is a flowchart showing a part of the processing contents of the control bag W1. In the figure, 1, 1'...control device, 2.3...register file, 4,5...address register, 6.
・・Zero check circuit, 7.7°・・Zero register,
8... Leading zero detection circuit, 9... Leading zero register, 10t... Adder, 11... Zero count register, 12... Zero accumulation circuit, 13...
・Data conversion circuit, 21...AND circuit, 22...
Selector, 31... Inverter, 32... OR circuit. Block diagram of a large flow example of the present invention FIG. 1 From 6 '1'' A circuit diagram showing an example of the zero accumulation circuit 120a FIG. 2 A circuit diagram showing an example of the configuration of the data conversion circuit 13

Claims (1)

[Scope of Claims] In a data processing device that performs leading zero counting of numerical data consisting of a plurality of words, a plurality of words constituting the numerical data are input sequentially from the upper word, and the words included in the input words are a zero check circuit that checks whether or not all characters are zero and outputs a signal indicating the result; a zero register to which an input signal is set; an output signal of the zero register and an output signal of the zero check circuit. a zero accumulation circuit that outputs a signal to the zero register indicating whether or not the characters included from the most significant word to the word checked by the zero check circuit are all zeros by performing an AND with the zero check circuit; leading zero counting means for counting the number of zero digits from the most significant digit of the input word until a non-zero digit appears, and sequentially adding the number of digits for each word; If the word higher than the word input to the check circuit indicates that the word is not all zeros, counting of leading zeros by the leading zero count means is inhibited, and the output signal of the zero register is input to the zero check circuit. suppressing means for inputting the same word as the word inputted to the zero check circuit to the leading zero counting means if the word higher than the word inputted indicates that the word is all zero; It is characterized by comprising a control means for sequentially adding a plurality of words constituting the numerical data one word at a time starting from the upper word, and for controlling the set timing of the input signal of the zero register and the operation timing of the leading zero count means. data processing equipment.