JPH061445B2 - Checksum circuit in microcomputer - Google Patents

Description

The present invention relates to a microcomputer system,
The present invention relates to a checksum circuit in a microcomputer used to check the validity of transferred data when transferring a series of memory areas in blocks.

2. Description of the Related Art In a computer system, various methods have been proposed for determining whether or not there is an error in data transfer when reading information stored in a memory or storing information in the memory. The simplest one is a vertical parity method that checks transfer data bit by bit.

However, since this method focuses on bit information in 1-word or 1-byte data, word- or byte-unit transfer in so-called block transfer of multi-word or multi-byte data It is extremely difficult to detect an error accurately, and as a method for dealing with this, a cyclic redundancy check (Cyclic Redu) is used.
The nda-ncy check (CRC) method and the horizontal parity check method are known. In particular, the latter is the content of a parity word that is a cumulative sum of corresponding bits of a large number of words or bytes of data to be transferred. Is used as an information source for detecting transfer errors.
This is a well-known method also called a sum check method. Further, according to these methods, not only the transfer error that occurs during block transfer can be detected, but also the data identity can be checked between two subsequent block transfers. It is also possible to easily detect the destruction of the data contents that should be kept the same due to a program error or the like.

Therefore, in order to realize such a sum check method in a conventional computer system, particularly a microcomputer system, a checksum register for storing a parity word is externally attached as an input / output device of the system. Each time one word or one byte of data is transferred, the data content is also transferred to the checksum register, and at the end of a series of block transfers,
Since it was necessary to read the contents of the checksum register (Fig. 5), when executing this method,
Compared with the case where the checksum is not taken, the program steps (1), (3), and (6) in the figure become extra operations, and therefore the processing time required for transfer becomes extremely long, which is a serious problem. The drawbacks were inevitable. For example, in a system using an Intel 8086 microcomputer as a central processing unit,
When a checksum is not taken when performing a block transfer of 1024 bytes, by utilizing a repeat prefix instruction and a string operation instruction, about 51
The processing time of 30 clocks is sufficient, but when the checksum is taken, it is not possible to utilize each of the above high-speed instructions, and data is transferred to the external checksum register for each word (2 bytes). Combined with the cost,
A block transfer of the same number of bytes requires a processing time of about 17940 clocks.

Therefore, in view of the circumstances of the prior art, an object of the present invention is that no matter what type of transfer instruction is used, the address signal and the data are transferred in units of one word or one byte on the bus of the system. Paying attention to the fact that signals appear in time series, by connecting a full adder for sequentially adding this data signal bit by bit and a checksum register to the checksum register, hardware is added to the checksum register. Since the checksum of the data signal can be integrated via the CPU, the checksum can be taken with almost no extra processing time added to the central processing unit. It is to provide a checksum circuit in a computer.

Therefore, the structure of the present invention for achieving such an object is a full adder for adding data signals appearing in time series on a bus in a bit unit at the time of block transfer. And a checksum register that stores the output of the full adder and a driver that outputs the contents of the checksum register to the bus. The checksum register can read and erase the contents as an input / output device. In addition to the above, the gist is that an address decoder is provided so that an address range for which a checksum should be taken can be set.

With this configuration, when block transfer is performed, each word or byte, which is the transfer unit, is
Since the address signal and the data signal appear on the bus, the full adder operates in bit units of the data signal on the bus only when the content of the address signal is within the range set in the address decoder. By adding and accumulating the result in the checksum register,
A checksum for the block transfer can be obtained with almost no extra processing time, and the checksum obtained by reading and erasing the contents of the checksum register can be obtained. It is possible to perform reading by the central processing unit and initialization of the checksum register.

Example Hereinafter, an example will be described with reference to the drawings.

Checksum circuit 10 in microcomputer
Includes a full adder 13, a checksum register 14, a driver 15, and an address decoder 18 as main elements (FIG. 1).

The microcomputer system is a central processing unit (CP
U) 1, a memory unit 2, and one or more input / output devices 3 are connected by a system bus (hereinafter, simply referred to as a bus) 9 and are formed. , Connected to this bus 9.

The bus 9 is a data bus 9a and a control bus 9b.
And an address bus 9c, and a central processing unit 1,
Since the memory unit 2 or the input / output device 3 is connected via the bus 9, the data bus 9a, the data bus 9a, or the like each time data is transferred between these devices.
On the control bus 9b and the address bus 9c, predetermined data signals, control signals and address signals appear in time series. However, here, the data bus 9a is composed of 16 signal lines for simultaneously carrying 16-bit data signals D0 to D15, and the address bus 9c carries simultaneously 20-bit address signals A0 to A19. Further, the control bus 9b is composed of 20 signal lines, and the required number of signal lines is appropriate.

The full adder 13 is a 16-bit full adder, and its input is connected to the data bus 9 a of the bus 9 via the exclusive OR circuit 11 and the temporary register 12. That is, the lower 8 bits D0 of the data bus 9a
To D7 are input to the temporary register 12 via the exclusive OR circuit 11, and the upper 8 bits D8 to D15 are directly input to the temporary register 12, and the output of the temporary register 12 is directly input to the full adder 13. It is an input. The lower 8 bits of the address bus 9c excluding the least significant bit A0
Bits A1 to A8 are input to the exclusive OR circuit 11.

The checksum register 14 is a 16-bit register that receives the output of the full adder 13, and its output is
It is fed back to the full adder 13 and connected to the data bus 9a via the driver 15. However, in FIG. 1, from the data bus 9a, the exclusive OR circuit 11, the temporary register 12, the full adder 1 are connected.
3. In the circuits up to the checksum register 14 and the driver 15, the lower 8 bits D0 to D7 and the upper 8 bits D8 to D15 of the 16-bit data signal D0 to D15 are written as separate signal lines. .

The input / output port comparator 16 is connected to the address bus 9c.
Are connected. The lower 16 bits A0 to A15 of the address bus 9c are input to the input / output port comparator 16, and the input / output port setting switch 16a formed of a 16-bit dip switch is also input. The input / output control unit 17 together with the input / output control signals IOR and IOW from the bus 9b
Has been entered in. Further, the output of the input / output control unit 17 is connected to the checksum register 14 and the driver 15 as output signals S1 and S6, respectively.

An address decoder 18 is connected to the upper 3 bits A17 to A19 of the address bus 9c, and the refresh signal RFSH from the control bus 9b is also input to the address decoder 18. The output of the address decoder 18 is the memory read / write control signal MR from the control bus 9b.
An output signal S2 is input to the timing control unit 19 together with C and MWC, while an output of the timing control unit 19 is connected to the temporary register 12 and the checksum register 14.

The memory unit 2 includes a main body RAM 2a and a bank RAM
A plurality of bank RAMs 2 that can be switched via the window 2b
, and a bank register 2d for switching the bank RAMs 2c, 2c ... (FIG. 2). That is, in order to compensate for the shortage of the memory capacity of the main body RAM 2a, a plurality of bank RAMs 2c, 2c ... Are prepared, and any one of the bank RAMs 2c, 2c ... Is designated by the index set in the bank register 2d. , The main body RAM 2a and the designated bank RAM 2c are combined to complete a memory area (third part).
The central processing unit 1 can access the entire memory area consisting of the main body RAM 2a and the designated bank RAM 2c by the 20-bit address signals A0 to A19. However, all banks RAM2
It is assumed that the capacities of c, 2c ... Are the same, the address ranges AD1 to AD2 thereof are fixed, and match the address ranges AD1 to AD2 of the bank RAM window 2b. In this way, the main body RAM 2a and the plurality of bank RAMs 2c, 2c, ... Which can be arbitrarily switched complete a memory area accessible by the central processing unit 1, so that a RAM area directly accessible by the central processing unit 1 is created. , Can be expanded almost indefinitely.

The bank RAMs 2c, 2c ... And the bank RAM window 2
Each address range AD1 to AD2 with b is a round number, and the upper and lower limit values AD1 and AD2 of the address range AD1 to AD2 can be expressed by the upper 3 bits A17 to A19 of the address bus 9c input to the address decoder 18. I shall.

Now, it is considered that a checksum is taken in block transfer of an arbitrary file fb included in the designated bank RAM 2c to a file fm in an arbitrary area of the main body RAM 2a.

First, the central processing unit 1 executes an output instruction to erase the contents of the checksum register 14 and initialize it. That is, when an output instruction whose operand is the input / output port number set in the input / output port setting switch 16a is executed, the address signals A0 to A indicating the input / output port number are displayed on the address bus 9c.
Since 15 appears, the input / output port comparator 16
The coincidence of each input signal from the address bus 9c and the input / output port setting switch 16a is detected and its output is generated. On the other hand, since the output control signal IOW of the control bus 9b is generated by the execution of the output command, the input / output control unit 17 which receives the output of the input / output port comparator 16 and the output control signal IOW outputs the output signal S1. Is generated (the signal waveform S1 in FIG. 4, hereinafter simply referred to as (S1)).
The contents of are deleted and the checksum register 14 is initialized. If the checksum register 14 is initialized, its output is fed back to the full adder 13, so that the content of the full adder 13 is also cleared and initialized.

Then, the central processing unit 1 accesses the address of the first word of the file fb to transfer the first word of the file fb to the file fm. by this,
The address signals A0 to A19 corresponding to the address appear on the address bus 9c (A0 to A19). At this time, the bank R
It is assumed that the start address AD1 and the end address AD2 of the AM window 2b are set. Since the file fb is included in the bank RAM2c having the same address range AD1 to AD2 as the bank RAM window 2b, the address of the first word of the file fb is naturally the address range AD1 to AD2. Inside.
Therefore, the address decoder 18 generates the output signal S2 when the address signals A0 to A19 appearing on the address bus 9c are within the set address range AD1 to AD2, and the address signals A0 to A19 are If it is composed of a kind of combination of a comparator and a gate so as not to generate the output signal S2 when it is not included in the address range AD1 to AD2, the access to the first word of the file fb is performed. At this time, the output signal S2 of the address decoder 18 is obtained (S2), and this is input to the timing control unit 19.

On the other hand, since the instruction executed by the central processing unit 1 to access the first word of the file fb is a memory read instruction for reading the content of the word of the file fb, the memory read of the control bus 9b is performed. The control signal MRC appears (MRC). The timing control unit 19 outputs the output signal S of the address decoder 18.
2 and the memory read control signal M of the control bus 9b
RC and the output signal S3 is generated (S3),
This initializes the temporary register 12.

As a result of execution of the memory read instruction, the address bus 9c
Since the above address signals A0 to A19 and the memory read control signal MRC of the control bus 9b are both supplied to the memory unit 2 via the bus 9, the memory unit 2 responds to this by the address concerned. Memory contents, that is, the contents of the first word of the file fb,
The data signals D0 to D15 are output onto the data bus 9a (D0 to D15). The lower 8 bits D0 to D7 of the data signals D0 to D15 are supplied to the exclusive OR circuit 11 together with the lower 8 bits A1 to A8 on the address bus 9c excluding the least significant bit A0 of the address signals A0 to A19. It is input, and the exclusive OR between corresponding bits is obtained here, and the resulting 8 bits and the data signal D
The upper 8 bits D8 to D15 of 0 to D15 are both input to the temporary register 12.

The setting of the input data to the temporary register 12 is performed by another output signal S4 of the timing control unit 19. That is, it is assumed that the output signal S4 is output at the timing of the return of the memory read control signal MRC (S4), and at that time, the data signals D0 to D15 exist as defined signals on the data bus 9a. ing. In this way, the data set in the temporary register 12 by the output signal S4 includes the upper 8 bits D8 to D15 of the data signals D0 to D15 and the lower 8 bits D0 to D7 of the data signals D0 to D15. It consists of a combination of the address signals A0 to A19 representing the address of the corresponding word of the stored file fb and those modified by the lower 8 bits A1 to A8 excluding the least significant bit A0.

Since the data set in the temporary register 12 is input to the full adder 13 as it is, full addition is performed with the current contents of the full adder 13, but the full adder 13 first The checksum register 14 is initialized by the output signal S1 from the input / output control unit 17, and the result is fed back.
All the bits of the contents are cleared, and therefore, the contents of the temporary register 12 are directly transferred to the full adder 13 here.

After outputting the output signal S4, the timing control unit 19 sends another output signal S5 to the checksum register 14 after a delay time Ta (S5), and the checksum register 14
Takes in and stores the contents of the full adder 13 at this timing. However, the delay time Ta is a delay time that allows for the calculation time of the full adder 13. Furthermore, since the contents of the checksum register 14 are fed back to the full adder 13 as they are, the full adder 13
The contents are retained even in.

The central processing unit 1 operates in parallel with the above-described operation of the checksum circuit 10 to perform data signal D0 to D15 on the data bus 9a.
Is read in a predetermined register (not shown) in the central processing unit 1.

Thus, the next instruction executed by the central processing unit 1 is a memory write instruction for storing the read data D0 to D15 in the first word of the file fm. In response to this memory write command, the address signals A0 to A0 corresponding to the word of the file fm are placed on the address bus 9c.
A19 appears, but address signals A0-A at this time
Reference numeral 19 indicates a word in the file fm included in the main body RAM 2a, and therefore, this is the address range AD1 to AD set in the address decoder 18.
Not between D2 and therefore address decoder 18
Does not generate its output signal S2 in response to this memory write command. Therefore, the timing control unit 19 does not generate any of its output signals S3, S4, S5, and therefore the checksum circuit 10 does not operate as a whole. However, during this time, it goes without saying that data is transferred from the central processing unit 1 to the word at the predetermined address of the file fm, and the operation of the memory write command is executed.

Subsequently, the central processing unit 1 executes a memory read instruction to transfer the second word of the file fb. The operation of the checksum circuit 10 at this time is exactly the same as that in response to the execution of the memory read instruction of the first word to be transferred. However, at the time when the data is set in the temporary register 12 by the output signal S4 from the timing control unit 19, as described above, the full adder 13 has the checksum register immediately after the execution of the previous memory read instruction. Since the contents of 14 are held, the calculation result of the full adder 13 this time becomes the cumulative addition result of the previous time and this time, and this cumulative result is set in the checksum register 14, and this is the full addition. It is fed back to the container 13 and held.

Subsequently, for the memory write instruction executed by the central processing unit 1, as described above, the checksum circuit 10
Does not respond at all.

When the transfer of all the words of the file fb is completed by repeating the above operation, the lower 8 bits D0 to D7 of all the words of the file fb are stored in the checksum register 14 as the contents of the address of each word. A checksum of data is obtained which is a combination of the exclusive OR of the lower 8 bits A1 to A8 excluding the lower bit A0 and the upper 8 bits D8 to D15.

Then, in the central processing unit 1, the input instruction having the input / output port number set in the input / output port setting switch 16a as an operand is executed. In response to this, the input / output port comparator 16 generates an output and the input control signal IOR of the control bus 9b appears, so that the input / output control section 17 responds to each of these signals by
The output signal S6 is generated to drive the drive 15. Since the contents of the checksum register 14 are input to the driver 15, the driver 15 receives the output signal S6 from the input / output control unit 17 and outputs the contents of the checksum register 14 onto the data bus 9a. And, therefore,
The central processing unit 1 can read the checksum stored in the checksum register 14 as a result of the input instruction.

The operation of the checksum circuit 10 described above is performed by the main body RAM 2a.
The same applies to the block transfer from the file fm in the bank to the file fb in the bank RAM 2c. Therefore, at this time also, the checksum is accumulated in the checksum register 14, and the central processing unit 1 and the driver 15 The result can be read via the data bus 9a. However, at this time, the address decoder 18 still generates the output signal S2 only for the address of each word of the file fb which is the range of the address ranges AD1 to AD2, and therefore the address decoder 18 outputs the signal. The signal S2 is generated and the checksum is accumulated in the checksum register 14 not at the time of executing the memory read instruction for the file fm, but at the file f.
This is when the memory write instruction for b is executed. Therefore,
The timing control unit 19 is operated to output the output signal S3,
It is the memory read control signal MRC that causes S4.
Instead, the memory write control signal MWC is used, and the operation is different. Generally, the time length of the data signals D0 to D15 appearing on the data bus 9a is longer when the memory write instruction is executed than when the memory read instruction shown in FIG. 4 is executed. Circuit 10
As for the operation of, the present time, which responds to the memory write instruction, has a large margin in terms of timing.

As described above, at the time of block transfer between the files fb and fm, the checksum can be obtained in the checksum register 14 regardless of the data transfer direction. If the checksum obtained during the transfer from the file fm to the file fb is stored and then compared with the checksum obtained during the reverse transfer, these checksums can be easily obtained. Whether or not there is a transfer error during block transfer, or 2
It is possible to detect the presence or absence of data identity during one block transfer.

The refresh signal RFSH input to the address decoder 18 does not directly relate to the operation of the checksum circuit 10, but when the dynamic RAM is used as a memory element forming the memory unit 2, the addresses AD1 to AD2 are used. Even if the memory refresh operation is performed on the area within the range, it is inputted for the purpose of prohibiting the operation of the address decoder 18 so that the address decoder 18 does not carelessly output the output signal S2.

In the embodiment described above, the exclusive OR circuit 11
Are the lower 8 bits D0 to D7 of the data signals D0 to D15.
And the lower 8 bits A1 to A8 of the address signals A0 to A19 excluding the least significant bit A0 are exclusive ORed between the corresponding bits. Here, with respect to the address signals A0 to A19, the least significant bit A0 is excluded because the bit is used as information for switching memory access in word units and memory access in byte units of the 8086 series manufactured by Intel Corporation. This is because it is assumed that the central processing unit 1 is used. Generally, the address information to be input to the exclusive OR circuit 11 is the bank RA.
It is preferable to use an arbitrary lower number of bits enough to cover the memory capacity of M2c. That is, the exclusive-OR circuit 11 modifies the data signals D0 to D15 with a part of the address signals A0 to A19, so that an exchange error in units of words (addresses of specific words are exchanged during the block transfer). The purpose is to detect the occurrence of a type error (hereinafter the same)), but an extreme error occurs in which one address involved in this commutative error exceeds the range of the bank RAM 2c. In this case, it can be easily detected by a separately prepared wordware or software protection method. However, when the number of bits of the exclusive OR circuit 11 is increased, the data signals D0 to D0
It goes without saying that all bits of D15 may be modified, and further, the contents of the logical operation in the exclusive OR circuit 11 are changed to other arbitrary contents of the logical operation in bit units. You can do it.

Address range AD1 to be set in the address decoder 18
AD2 is the bank RAM window 2b or the bank RAM2
c start address AD1 and end address AD2
Is used as it is, but instead of this, the file f to be the transfer source or the transfer destination is used.
Using the start and end addresses of b,
It is also possible to variably set this for each transfer. According to this, when an exchange error that deviates from the range of the file fb occurs, the address decoder 18
However, since the output signal S2 is not generated, the error can be surely detected as a checksum error without depending on the modifying operation of the data signals D0 to D7 by the exclusive OR circuit 11.

In the above description, the data transfer between the files fb and fm is described as being realized by repeating the transfer instruction in units of one word, but the operation of the checksum circuit 10 is as follows: a high-speed repeat prefix instruction and a string. There is no change when using the operation commands and. That is, even at that time, the contents and order of the signals appearing on the address bus 9a, the control bus 9b, and the data bus 9c in time series are the same as those described above.

Further, in this embodiment, the address signals A0 to A1
Although 9 is composed of 20 bits, the data signals D0 to D15 are composed of 16 bits, and the transfer operation is explained in word units, the signals are composed of any other number of bits. Furthermore, even if the transfer operation is performed in byte units, the present invention can be applied as it is without any change in its gist.

EFFECTS OF THE INVENTION As described above, according to the present invention, a full adder for accumulatively adding the data signals appearing on the bus in time series on a bit-by-bit basis and storing the output of the full adder during block transfer. A checksum register and a driver that outputs the contents of the checksum register to the bus are provided, so that the contents of the checksum register can be read and erased, and the address range for taking the checksum is set. By providing the address decoder, the full adder and the checksum register can branch and input the data signal appearing on the bus and integrate the checksum without consuming any processing time of the central processing unit. Accurately, without imposing an extra processing burden on the central processing unit, as in the case of software processing
The checksum can be obtained, which is an extremely excellent effect.

In addition, as long as the data signal and the address signal appear in time series on the bus for each transfer unit consisting of a word unit or a byte unit, a high-speed operation such as a combination of a repeat prefix instruction and a string operation instruction can be performed. There is also an excellent effect that the checksum can be surely obtained even when the block transfer is performed, and that the high speed performance of these instructions is not impaired at this time.

In addition, since all input / output signals can be connected to the bus of the microcomputer system, it can be used for existing or standard configuration systems without special memory check circuits or memory protection functions. ,
There is also a practical effect that it can be added very easily.

[Brief description of drawings]

1 to 4 show an embodiment, FIG. 1 is an overall block diagram, FIG. 2 is a conceptual diagram of a memory unit configuration, FIG. 3 is a conceptual explanatory diagram of block transfer, and FIG. It is a waveform explanatory view. FIG. 5 is a program flow chart for explaining the conventional technique. A0 to A19 ... Address signal D0 to D15 ... Data signal 2b ... Bank RAM window 9 ... Bus 13 ... Full adder 14 ... Checksum register 15 ... Driver 18 ... Address decoder

Claims (3)

[Claims] 1. A full adder for adding data signals appearing on a bus in time series on a bit-by-bit basis during block transfer, a checksum register for storing the output of the full adder, and a checksum register for the checksum register. The checksum register is capable of reading and erasing contents as an input / output device having an arbitrary input / output port number, and having a driver for outputting the contents to the bus. The address signal appearing on the bus is provided with an address decoder for setting
A checksum circuit in a microcomputer, wherein the checksum is taken only when it is within a range set by the address decoder. 2. The checksum in a microcomputer according to claim 1, wherein the full adder modifies the data signal on the bus by an address signal on the bus and adds the data signal. circuit. 3. The checksum circuit in the microcomputer according to claim 1, wherein the address decoder sets an address range corresponding to a bank RAM window.