JPS6336036B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a method for detecting stains in images such as characters and calligraphy, and particularly relates to a method for detecting stains when an image such as characters formed of a contour line pattern (contour line pattern image) is contaminated. The "contour line pattern image" as referred to in the present invention is one in which the ordinary image shown in FIG. 1a is represented by a group of curved lines equidistant from the contour, as shown in FIG. First, a method for creating a contour line pattern will be briefly explained. FIG. 2 shows a block diagram of the contour line pattern image creation device. In this example, the image is made up of 2048 pixels in the main scanning direction, but it is clear that the present invention is not limited to this. 1 and 2 are each one (frame)
A and B memories capable of storing all pixels of the image;
3 is a clock and control signal generator, 4 is a flip-flop, 5 and 6 are each 2046-bit shift registers, 7 to 9, 51, 52, 61, and 62 are each 1-bit shift registers, 10 is a 2-bit counter, and 11 is an address. Counter 12 is an address converter. When the start (START) signal is input, the clock and control signal generator 3 sets the initial (INITIAL) signal to "1" only during the period of scanning the entire area of the A and B memories 1 and 2. This signal “1” passes through OR gates O1 and O2 to memory 1,
2, both memories A and B are in write mode. At the same time, a clock signal is input to the address counter 11 to sequentially designate each address in the A and B memories. At this time, new data (DATA) is supplied to A memory 1 via AND gate A1, so new read data is stored in A memory. On the other hand, the input of B memory 2 has an initial signal “1”.
Since the signal "0" which is inverted by the inverter I is input, the entire area of the B memory is cleared. Clock and control signal generator 3 also generates a RESET signal to reset all shift registers, flip-flops and counters. The operation of the apparatus shown in FIG. 2 will now be described assuming that an image as shown in FIG. 3a is stored in the A memory 1 as new data. First, the address counter 11 is reset and the initial signal becomes "0". As a result, the A and B memories are switched to read mode. address counter 1
The count value of 1 increases again in sequence to designate the read address of the A and B memories. However, the address specification in this case is A memory 1.
address converter 1 so that the one for B memory 2 precedes the one for B memory 2 by one scanning line.
2 is adjusted. In other words, the specified address for A memory 1 is AD _a , and that for B memory 2 is AD _b.
Then, in this example, the address AD _a is [AD _b +
2048]. The data stored in the A memory is sequentially read out and input to the shift register 7, and then sequentially transferred to the shift registers 8→9→6→61→62→5→51→52. Signal SR of the pixel being processed
When 0 is in the shift register 61, the upper left, right above, upper right, left side, right side, lower left, right below,
As shown in FIGS. 2 and 4, the signals of the pixels at the lower right positions are the most significant digits of shift registers 7, 8, and 9, shift register 6, shift register 62, and shift register 5, respectively. most significant digit,
SR1 to SR8 from shift registers 51 and 52
It is output as . If SR0 is "0" at this time, AND gates A2 and A3 are closed, so the W/R of each memory
The signal becomes "0". That is, since A and B memories 1 and 2 are in read mode, B memory 2
The content of is not changed and remains at "0".
On the other hand, when SR0 is "1", it is checked by the NAND gate NA whether the read signals SR1 to SR8 of the surrounding points shown in FIG. 4 are all "1". If they are all "1", the output becomes "0" and AND gates A2 and A3 are closed, and the contents of B memory 2 are not changed and kept at "0" as before. However, when all of SR1 to SR8 are not "1", that is, when at least one of them is "0" (white), the output of NAND gate NA becomes "1" and AND gates A2 and A3 are opened. It will be done. As a result, the W/R signal of A memory 1 becomes “1”, that is, it is in write mode, but its IN
Since the signal is "0", in the A memory 1, the "1" at the processing target point is erased and becomes "0". Points that satisfy the above conditions are part of the contour,
All such points will be erased. Since the 2-bit counter 10 is reset to "00" at the beginning of the processing operation, the NOR gate
The output of NOR is "1", and therefore the output of AND gate A3 is also "1". Therefore, B
Memory 2 enters the write mode, and at this time the initial signal is "0" and the IN signal of B memory 2 is "1", so "1" is written to the address of B memory corresponding to SR0 in Figure 4. be included. If you perform the above operations for one frame,
The image in Figure 3a stored in the A memory 1 is converted into a thin shape with its outline shaved off as shown in Figure 3c, while the image in the B memory 2 has a contour line corresponding to the image in Figure 3a. The image shown in Figure b is stored. During the above operation, the data read from A memory 1 contained one or more "1"s, so flip-flop 4 was placed in the set state. Next, the same processing as described above is performed on the image shown in FIG. Closed. Therefore, even if a point (bit) on the contour is detected, writing to the B memory 2 is not performed. However, the outline of the stored image in the A memory 1 is removed by one pixel. Furthermore, when the same operation is repeated and the contents of the 2-bit counter become "10" or "11", AND gate A3 is closed in the same way, so the outline is not written to B memory 2. The stored image in the A memory 1 is only narrowed as shown in FIG. 3d. In the fourth frame, the 2-bit counter 10 becomes "00" again, so as is clear from the above description, the outline of the image stored in the A memory 1 at that time is stored in the B memory 2. Therefore, the stored images in the A and B memories at this time become as shown in e and f in FIG. 3, respectively. When the same processing is performed again, all the stored contents of the A memory 1 become "0", and the flip-flop 4 remains in the reset state when the next frame processing is completed. The output of the flip-flop 4 at this time is supplied to the clock and control signal generator 3 to stop the processing operation. The processed image (such as the one shown in Figure 3 f) is stored in the B memory 2, so if it is supplied to a known suitable output device (for example, a raster scan printer, etc.), a contour line pattern will be created. A transformed visible image can be obtained. Contour line pattern images created as described above often become smudged during subsequent handling, are intentionally tampered with, or are smeared on reproduced images obtained by copying them. . The present invention relates to a method for detecting dirt or tampering as described above, and further relates to a method for erasing portions determined to be dirt or tampering to obtain a clean reproduced copy image. FIG. 5 is a block diagram of one embodiment of the present invention.
1 to 28 are 2039-bit shift registers, 31 to 28 are 2039-bit shift registers,
Reference numeral 39 denotes a 9-bit shift register, which are successively connected in series as shown. First, 2
An image signal in value format is input to each of the shift registers. Here, we assume that one scanning line consists of 2048 bits (pixels), as mentioned above.
The mutual positional relationship of the information in each stage of the shift register in FIG. 5 matches that on the input original image. It goes without saying that the total number of bits in one scanning line is not limited to the above value. First, assume that the point to be processed P ₀ stored in the fifth digit of the shift register 35 is black (“1”),
A method for determining whether this point is normal information or dirty information will be described. As is clear from Figure 6, if point P ₀ is part of the contour line pattern image, it is impossible for all of the surrounding points P ₁ to _{P 8} to be black (“1”). Therefore, equation (1) should not hold. Note that "." in formula (1) indicates a theoretical product. P ₀ , P ₁ , P ₂ , P ₃ , P ₄ , P ₅ , P ₆ , P ₇ , P ₈ = 1
...(1) Therefore, in the AND circuit 41 of FIG. 5, the above (1)
When the formula is calculated and the output becomes "1", each of these points P ₀ to P ₈ is regarded as dirty, and the output (reset signal) R1 is used to read the contents of the shift register corresponding to each of these points. Reset. This removes dirt. However, when attempting to detect and erase dirt as shown in Figure 7a ("1" in the figure represents dirt), equation (1) holds true only at the three points marked O. , and equation (1) does not hold in other respects. Therefore, stains cannot be determined at the three points marked with the symbol "1" in b of the same figure, and the stains remain without being erased. By the way, if the processed point P ₀ is black (“1”) but is erased as noise, a point 1 bit outside of the 8 points P ₁ to _{P 8}
Since P ₉ to _{P 24} (see FIG. 6) are white (“0”) or noise, this region can also be set to “0” based on the above determination. For this purpose, in the embodiment of FIG. 5, the reset output R1 from the AND circuit 41 is supplied directly or via the OR circuits 42 and 43 to the corresponding stage of each shift register 33 to 37, and the information on the position is transmitted. It is reset to "0". Through the above processing, it is possible to detect and erase relatively large stains. however,
A narrow linear stain of two dots (pixels) or less, as shown by the hatched area in the upper half of FIG. 8, cannot be detected or erased by the above processing. Note that the diagonally shaded area in the lower half of FIG. 8 is the area forming the original contour line pattern. A method for detecting such linear stains will be described below. In Figure 9, if the point P ₀ to be processed is black (“1”) and this point P ₀ is part of the contour line pattern, then from the inherent properties of the contour line pattern shown in Figure 3 f, As can be seen, at least one bit of white adjacent to point P ₀ in at least one direction, above and below or to the left and right,
There should be at least one bit of black next to that. More specifically, for example, black and white continue upward from the processing point P ₀ in any of the manners as illustrated in the left half (A) to (E) of Table 1. It should be arranged.

[Table] When the arrays (A) to (E) are arranged above, all of the discriminant logical expressions shown in the right half of Table 1 become "1".
Note that "∨" in Table 1 represents a logical sum. Also, (f) shows for comparison the case where P ₀ is determined to be dirty, and the discriminant logical expression for this case is "0". The arrangement relationship of the black and white dots as described above is the same not only in the downward direction but also in the left and right directions. Therefore, in the case described above, the following equations (2) to (5) hold true for each direction. P ₀・(P ₂₆ ∨P ₂₇ )・₁₁・₂ = 1 ...(2) P ₀・(P ₃₀ ∨P ₃₁ )・₇・₂₂ = 1 ...(3) P ₀・(P ₂₈ ∨P ₂₉ )・₄・₁₆ = 1 …(4) P ₀・(P ₃₂ ∨P ₃₃ )・₅・₁₇ = 1 …(5) Therefore, do the above equations (2) to (5) hold? If any one of them is true, it is determined that the point to be processed P ₀ is part of the contour line pattern and it is left as is, and if none of equations (2) to (5) are true, then should be determined as noise and erased. The logic circuit groups 44 to 56 in FIG. 5 perform the above detection and erasing operations. As is clear from the figure, the operation of equation (2) is performed by, for example, an OR circuit 44, a NAND circuit 45, and an AND circuit 46. It will be easily understood that the other logic circuit groups perform the operations of equations (3) to (5), respectively. Finally, we will explain a method for detecting and erasing very small stains. In FIG. 6, regarding n consecutive dots, for example, 3 dots P ₄ -P ₀ -P ₅ , the black and white of 12 surrounding dots are determined, and if there is no black ("1") among them, then the 3 dots can be considered as dirt. That is, if the logic of equation (6) is executed and this holds true, the three points P ₄ , P ₀ ,
_P5 can be determined as dirt and can be erased. P ₁ ∨P ₂ ∨P ₃ ∨P ₁₅ ∨P ₁₇ ∨P ₁₉ ∨P ₈ ∨P ₇ ∨P ₆ ∨P ₁₈ ∨
P ₁₆ ∨P ₁₄ =0 (6) This logical operation is executed by the NOR circuit 57 in FIG. That is, when the above formula (6) holds true, the output of the NOR circuit 57 becomes "1", and this is sent to the shift register 35 as the reset signal R3.
Since it is added to the P ₄ , P ₀ , and P ₅ digits, the information at these positions is reset to "0". In this case, in the embodiment shown in FIG. 5, it goes without saying that the inputs of each logic circuit should be taken out from the corresponding digits of the shift register, and also from the frame memory (not shown) or the digits shown in FIG. It is best to provide the same second shift register group and reset the stored contents by supplying reset signals R1, R2, etc. to the corresponding addresses of these frame memories or the corresponding digits of the second shift register group. good. When the above processing is performed on all pixels of the contour line pattern image, relatively large stains, long thin line stains, and very small stains are detected and erased, so a high-quality, clean image is reproduced. At the same time, it becomes easier to detect tampering with the original image. Note that when dirt is erased by the above operation, pixels that were originally part of the contour line pattern may also be erased, but after performing the processing of the present invention, for example, 1977-
If the missing portion is reproduced according to the method disclosed in Japanese Patent No. 111976, it is possible to finally reproduce a complete contour line pattern image without any stains. Furthermore, in the above, we have described the case where both the width and interval of the contour lines are 1 bit, but even when these values are arbitrary bits, it is only necessary to change the pattern of the comparison area around the test dot. That is clear. Furthermore, although the above example has shown an example in which the present invention is implemented by a combination of logic elements, it is clear that similar operations can also be realized by appropriately programming a computer.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a normal image and an image with a contour line pattern, which is the processing target of the present invention. FIG. 2 is a block diagram of an apparatus for creating an image with a contour line pattern.
FIG. 4 is a diagram for explaining its operation, FIG. 5 is a block diagram of one embodiment of the present invention, and FIGS. 6 to 9 are diagrams for explaining its operation. 21-28, 31-39...shift register,
41-57...Logic elements.

Claims (1)

[Claims] 1. A step of reading and storing a contour line pattern image image by image in a binary signal format of "1" and "0"; a step of detecting the presence or absence of a pixel for each pixel, and a step of detecting the presence or absence of a pixel on a pixel-by-pixel basis;
A step of determining whether or not there is a pattern in which the most recent planned number of adjacent bits is “0” and the next scheduled number of adjacent bits is “1” among the seed patterns; A method for detecting dirt in a contour pattern image, comprising the step of determining that a test dot is not dirt if there is at least one pattern that satisfies the pattern.