JPS6338741B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for creating an image represented by a contour line pattern from an original image such as a character or image recorded in a binary format. To be more specific, the first
By connecting points equidistant from the contour of a normal input image as shown in Figure A to create a contour line-like curve, and repeating this process, a contour line pattern as shown in Figure 1B can be created. The present invention relates to a device for creating a captured image.

One embodiment of the invention is shown in FIG. In this example, it is assumed that the image consists of 2048 pixels in the main scanning direction, but it is clear that the present invention is not limited to this. 1 and 2 are A and B memories each capable of storing all pixels of one image (frame); 3 is a clock and control signal generator; 4 is a flip-flop; 5 and 6 are each 2046-bit shift registers; 7 to 9 ,5
1, 52, 61, and 62 are 1-bit shift registers, 10 is a 2-bit counter, 11 is an address counter, and 12 is an address converter.

When the start (START) signal is input, the clock and control signal generator 3 sets the initial (INITIAL) signal to "1" only during the period when all areas of the A and B memories 1 and 2 are scanned. Since this signal "1" is applied to memories 1 and 2 via OR gates O1 and O2, both memories A and B are in write mode. At the same time, a clock signal is input to the address counter 11 to sequentially designate each address in the A and B memories.

At this time, new data (DATA) is supplied to A memory 1 via AND gate A1, so new read data is stored in A memory. On the other hand, the input of B memory 2 has an initial signal “1”.
is inverted by the inverter I and a signal "0" is input, so that the entire area of the B memory is cleared.
Clock and control signal generator 3 also generates a RESET signal to reset all shift registers, flip-flops and counters.

Now, assuming that an image as shown in FIG. 3a is stored in the A memory 1 as new data, the operation of the apparatus shown in FIG. 2 will be explained. First, the address counter 11 is reset and the initial signal becomes "0". As a result, the A and B memories are switched to read mode. address counter 1
The count value of 1 increases again in sequence to designate the read address of the A and B memories.

However, the address specification in this case is A memory 1.
address converter 1 so that the one for B memory 2 precedes the one for B memory 2 by one scanning line.
2 is adjusted. In other words, the specified address for A memory 1 is AD _a , and that for B memory 2 is AD _b.
Then, in this example, the address AD _a is [AD _b +
2048].

The data stored in the A memory is sequentially read out and input to the shift register 7, and then sequentially transferred to the shift registers 8→9→6→61→62→5→51→52. Signal SR0 of the pixel being processed
is in the shift register 61, the signals of the pixels at the top left, right above, top right, left side, right side, bottom left, right below, and bottom right of the screen are shown in FIGS. 2 and 4. Shift registers 7, 8, 9, the most significant digit of shift register 6, shift register 62, the most significant digit of shift register 5,
The shift registers 51 and 52 output them as SR1 to SR8.

At this time, if SR0 is “0”, AND gate A
2. Since A3 is closed, the W/R signal of each memory becomes "0". That is, since the A and B memories 1 and 2 are in the read mode, the contents of the B memory 2 are not changed and are kept at "0". on the other hand,
If SR0 is "1", the NAND gate NA is used to check whether the read signals SR1 to SR8 of the surrounding points shown in FIG. 4 are all "1". All “1”
If so, the output becomes "0", AND gates A2 and A3 are closed, and B memory 2 is output as before.
The content of is not changed and remains at "0".

However, when all of SR1 to SR8 are not "1", that is, when at least one of them is "0" (white), the output of NAND gate NA becomes "1" and AND gates A2 and A3 are opened. It will be done. As a result, the W/R signal of A memory 1 becomes “1”, that is, it is in write mode, but its IN
Since the signal is "0", in the A memory 1, the "1" at the processing target point is erased and becomes "0". Points that satisfy the above conditions are part of the contour,
All such points will be erased.

Since the 2-bit counter 10 is reset to "00" at the beginning of the processing operation, the NOR gate
The output of NOR is "1", and therefore the output of AND gate A3 is also "1". Therefore, B
Memory 2 enters the write mode, and at this time the initial signal is "0" and the IN signal of B memory 2 is "1", so "1" is written to the address of B memory corresponding to SR0 in Figure 4. be included.

If you perform the above operations for one frame,
The image in Figure 3a stored in the A memory 1 is converted into a thin shape with its outline shaved off as shown in Figure 3c, while the image in the B memory 2 has a contour line corresponding to the image in Figure 3a. The image shown in Figure b is stored.

During the above operation, the data read from A memory 1 contained one or more "1"s, so flip-flop 14 was placed in the set state.

Next, the same processing as described above is performed on the image shown in FIG. Closed. Therefore, even if a point (bit) on the contour is detected, writing to the B memory 2 is not performed. However, the outline of the stored image in the A memory 1 is removed by one pixel. Furthermore, when the same operation is repeated and the contents of the 2-bit counter become "10" or "11", AND gate A3 is closed in the same way, so the outline is not written to B memory 2. This is not done, and the stored image in the A memory 1 only becomes thinner as shown in FIG. 3d.

In the fourth frame, the 2-bit counter 10 becomes "00" again, so as is clear from the above description, the outline of the image stored in the A memory 1 at that time is stored in the B memory 2. Therefore, the stored images in the A and B memories at this time become as shown in e and f in FIG. 3, respectively. When the same processing is performed again, all the stored contents of the A memory 1 become "0", and the flip-flop 4 remains in the reset state when the next frame processing is completed. The output of the flip-flop 4 at this time is supplied to the clock and control signal generator 3 to stop the processing operation.

The processed image (such as the one shown in FIG. 3 f), that is, a group of contour lines with a gap of one pixel or a blank space between adjacent contour lines, is stored in the B memory 2, so it is known that By supplying the image to a suitable output device (for example, a raster scan type printer, etc.), a visible image converted into a contour line pattern can be obtained.

The contour line pattern image created by the present invention is
In addition to being useful for reproducing missing parts of stored images (Japanese Patent Application No. 55-14708), removing dirt and noise from reproduced images (Japanese Patent Application No. 14706-1987), etc., which was filed on the same date,
Lettering that extracts only the outline from ordinary letters, etc., and the center part (ridge) of the strokes of ordinary letters, etc.
It is also useful for so-called "bone extraction" (as a preprocessing for optical character reading).

In addition, above we have described an example of converting the image part into a contour line pattern, but the same process can be performed on the ground (background) of the image by inverting the black and white, and the interval between the contour line patterns can be changed using AND gate 3. It will be readily understood that this can be easily changed by changing the size of the input 2-bit counter and the circular arithmetic format of its output.

Furthermore, although the present invention has been described above as an example of implementing it by combining unit logic elements, it is clear that it can also be implemented by appropriately programming an electronic computer or the like.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of an original image and a contour patterned image obtained by the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, and FIGS. 3 and 4 illustrate its operation. It is a figure for explaining. 1...A memory, 2...B memory, 3...clock and control signal generator, 5-9, 51, 5
2, 61, 62...shift register, 10...2
Bit counter, 11...Address counter, 1
2...Address converter.

Claims (1)

[Claims] 1. Two frame memories A and B capable of storing all the image information of one document, and each pixel to be processed included in one frame read from memory A.
means for detecting information on surrounding pixels; means for determining whether or not the pixel to be processed belongs to the contour portion of the image based on the information detected by the means; and the pixel determined to be the contour portion. a means for writing each contour line formed by a set of pixels into a memory B with an interval of at least one pixel between adjacent contour lines; 1. A high-level line pattern image creation device comprising: means for outputting, recording and displaying information stored in memory B; and a control section controlling processing of each of the means.