JPS633514A - Frequency divider - Google Patents

Abstract

PURPOSE:To obtain an odd number frequency division waveform whose duty ratio is 50% by combining outputs of two counters counting clocks whose phases are shifted by 180 deg. to each other. CONSTITUTION:In putting '1' to a NAND 11 and '0' to ORs 4, 5 and a NAND 13 from the output of a decoder 12, counters 1, 2 count '2' then load '0'. The counters 1, 2 are simultaneously cleared then keep counting clocks whose phases are deviated by 180 deg. each other, respectively. Thus, an output QB of the counter 1 counting the advancing clock and an output QA of the counter 2 counting the retarded clock are ORed by the OR 5 and the result is extracted by a selector 9, resulting that a 1/3 frequency division output waveform whose duty ratio is 50% is obtained. Inputting '0' to the NAND 11 and '1' to the NAND 13 and the OR 5 from the decoder 12, and selecting the output of an OR 7, a 1/5 frequency division output is obtained.

Description

[Detailed description of the invention] [Technical field〕 The present invention relates to a clock frequency divider.

[Conventional example] Conventionally, this type of installation has progressed to one-chip, and there are many products that can programmably change the frequency division ratio. ), the duty ratio does not reach 50% when all odd number divisions are performed. Here, in order to obtain a waveform with 50% duty, divide the frequency twice by an odd number, and then
A configuration such as frequency division had to be adopted, and a separate circuit such as an oscillator had to be configured. Furthermore, when using a frequency-divided clock manually inputted from the outside, there is a problem in that if the frequency is divided by an odd number, it is impossible to obtain a clock with an accurate duty of 50%.

[Objective] The object of the present invention is to eliminate the drawbacks of the above conventional example, and
The object of the present invention is to provide a frequency divider that can supply a frequency-divided waveform with a duty of 50%.

[Example] An example of the present invention will be described in detail below with reference to the drawings. FIG. 1° is a circuit diagram of a wooden embodiment. Here, 1.2 is a binary counter, and counter 2 has an inverter 3.
The inverted clock is manually inputted, and the count is performed with a delay of half a clock from the counter 1. Since these counters 1 and 2 must operate in unison, when a reset signal is input, they are mutually cleared and then begin counting. CR of 4 and 5 and AND13°NAN
DI 1 is used as a switch for determining the odd frequency division ratio shown in this embodiment, and a counter is loaded by ANDIO of these outputs. Here, if NAND II is set high and OR4, 5 and AND13 are set low, 1
．． When both counters 2 count up to 2, they are loaded to °゛O''.At this time, if we take the Qa ratio output of counter 1 and the QA ratio output 0R15 of counter 2, the duty is 3 which is 50%.
A divided clock is obtained. Also, set NAND II to low, A
Turn on ND13 and OR5 high and turn on both counters 1
．． By taking the Qc ratio output OR7 of 2, a 5-divided clock with a duty of 50% is obtained, and when NANDI 1 is set low,
When OR4 and OR5 are set low, AND13 is set high, and the Qc ratio output is ANDed, a 7-frequency divided clock with a duty of 50% is obtained. Next, OR4 and 5 are high, AND13, NA
When NDII is set low, NAND6 and 11 continue to output high, so the Q0 output of counter 1.2 becomes high, and loading is not performed until the inverter 14 output becomes low, so both counters 1 and 2 continues counting from 0 to 8. By ORing the Ql) output of counter 1 and the Qc ratio output of counter 2 at this time, a 9-frequency divided clock with a duty of 50% is obtained. The output mentioned above is decoder 1
2, it is controlled and obtained by 2-bit input data. Next, the actual operation will be explained.

Actual time charts are shown in FIGS. 2 and 3. 16 is the reference clock, 17.18° 19.25 is the output of counter 1, 20 is the inverted input of CLK16, 21, 22
, 23 and 26 are the outputs of the counter 2, and 24 is the output from the selector 11. 1-a is Q when set to 5 division. Showing the 8 power of ut27. Here, when the counter 1.2 counts up to 5, it is loaded with 1.

At this time, Qc output 19 of counter 1 and Qc of counter 2
When output 23 is ORed, it is a 5-divided output Q with a duty of 50%. A waveform of ut27 is obtained. 1-b is Q when set to frequency division by 7. The output of ut27 is shown. Here, when the counter 1.2 counts up to 7, the load sets 91 and starts counting again. At this time, if you AND the Qc output 19 of counter 1, the Q of counter 2, and the output 23, you will get an output Q divided by 7 with a duty of 50%. A waveform of ut27 is obtained. For the frequency division by 5 and the frequency division by 7, 1 is loaded at the time of loading. FIG. 3 shows output waveforms when frequency division by 3 and frequency division by 9 are accessed.

At this time, the set value at the time of loading is 0. First 1-
c is Q when frequency is divided by 3. At the output of u, 27, counters 1 and 2
will load when it counts up to 2.

At this time, QB +8 output of counter 1 and Q of counter 2
If you take ORI 5 of A21 output, the duty is 50%, which is 3.
Frequency division pressure Q. A waveform of ut27 is obtained. Also, in 1-D, Q when frequency is divided by 9. The output of ut27 is shown. Here, counters 1 and 2 count and load up to 8. At this time, by ANDing the Qo output 25 of counter 1 and the Qc output 23 of counter 2, a 9-frequency divided output Q with a duty of 50% is obtained.
. The waveform of ut27 is obtained.

In this example, frequency division by 3, frequency division by 5, frequency division by 7, frequency division by 9
Although the frequency dividing circuits are integrated into one, by configuring this circuit separately, it is possible to perform odd number division with a high frequency division ratio such as division by 15, division by 21, division by 27, etc. Further, in this embodiment, only the frequency divider is used, but by applying opposite clocks to these two counters, it is also possible to create a desired waveform.

In the above embodiments, a counter is used, but this can also be done by using a flip-flop or the like.

Next, other embodiments of the present invention are shown in FIGS. 4, 5, and 6.
This will be explained based on the diagram. FIG. 4 is a circuit diagram of another embodiment. Here, 51, 52, and 60 are binary counters, and a clock inverted by an inverter 53 is inputted to the counter 52, and the counter 52 performs counting with a delay of half a clock from the counter 51. Since these counters 51 and 52 must operate synchronously, when a reset signal is input, they are mutually cleared and then begin counting. The OR of 54 and 55 is used as a switch for determining the odd frequency division ratio shown in other embodiments, and the counter is loaded by the NAND 56 of this output. 0R5
5 high and on, Q of both counters 51.52. By taking the output 0R57, a 5-divided clock with a duty of 50% is obtained, and by setting both 0R54 and 55 low, Qc
When the specific output is ANDed, a 7-frequency divided clock with a duty of 50% is obtained. When 0R54 is set high, a frequency divided by 6 output is obtained. Here, this 6-divided output is one counter 5
Although it can be obtained with only 1, 0R54 is similarly placed in the counter 52 in order to synchronize the two counters as described above. The above-mentioned frequency-divided clock and reference clock are input to the selector 59, and only one selected or ψ is output. The output of this selector 59 is input to an asynchronous counter 60 and an output selector 61. Here, the clock manually input to the selector 61 is selected by the decoder 62, and the output from the selector 59 is directly inputted to the Q. ut6
You can output from 3. Further, the clock input to the counter 60 is frequency-divided within the counter 60, and the clock of that frequency division ratio is Q-divided according to the decoder 62. Output from ut63. The decoder 62 is connected to an 8-bit data bus, and can determine the frequency division ratio of the clock on the bus.

Actual time charts are shown in FIGS. 5 and 6. 64 is the reference clock 65.66° 67 is the counter 51
output, 68 is the inverted input of CLK64, 69, 70.7
1 is the output of the counter 52, and 72 is the output from the selector 61. 2-a is Q when set to 5 division. , shows the output of Jt72. Here, the counter 51
, 52 loads 1 when it counts up to 5. Q of the counter 51 at this time. When the output 67 and the Qc output cuff 1 of the counter 52 are ORed, the output Q divided by 5 with a duty of 50% is obtained.
. A waveform of ut72 is obtained. 2-b is Q when set to 7 frequency division. The output of ut72 is shown. Here counter 5
When 1.52 counts up to 7, it is loaded, sets 1, and starts counting again. Counter 51 at this time
Qc output 67 of counter 2 and Qc output cuff 1 of counter 2
If you take D, you will get a 7-divided output Q with a duty of 50%. ut72
A waveform of 2-c is a 6-divided output Q with a duty of 50%. The ut720 waveform is shown. Figure 6 shows selector 59
is a part of the output waveform of the counter 60 when the clock 64 is selected. 73, 74, and 75 indicate points when the decoder 62 is switched.

Here, 73 is a point at which the frequency division output is switched from 4 frequency division to 2 frequency division output, 74 is a point at which frequency division is switched from 2 frequency division to 8 frequency division, and point 75 is a point at which frequency division is switched from 8 frequency division to 16 frequency division. Here, if the clock 64 is already frequency-divided by hand, it becomes 52.54, 58.66 of the human clock.
A divided waveform can be obtained. By changing the combination of selector 59 and selector 61 in this way, a large number of frequency-divided clocks can be obtained.

Also, in other embodiments, the frequency is divided by 5, and the frequency is divided by 6, as in the case of this embodiment.
The frequency divider and 7 frequency divider circuits are combined into one, but by configuring these circuits separately, frequency divided clocks such as 35 frequency dividers, 42 frequency dividers, 70 frequency dividers, etc. can be obtained. Further, although the counter is basically configured this time, the counter may also be configured using a flip-flop.

E effect As explained above, by inputting inverted clocks to two counters and combining their outputs, it is possible to obtain an accurate odd-number divided waveform with a duty of 50%. .

[Brief explanation of the drawing]

Figure 1 is a variable odd frequency divider circuit diagram of this embodiment, Figures 2 and 3.
1, FIG. 4 is a variable frequency dividing circuit diagram of another embodiment, and FIGS. 5 and 6 are time charts of other embodiments. 1.2 is a binary counter, 3 is an inverter, 4,5
, 6, 10, 11, 13.14 are gates for creating the timing to rot the counters 1 and 2, 7, 8, 15.1
6 is a gate for taking each divided waveform, 9 is a selector, 12 is a decoder, 16 is a manual clock, 20 is an inverted clock, 17, 18, 19.25 is the output of counter 1, 21.22, 23. 26 indicates the output of the counter 2, and 27 indicates a waveform output to the outside.

Claims (1)

[Scope of Claims] A first counter that counts clocks, a second counter that inputs a clock that is inverted with respect to the clock that is input to the first counter, and from the first counter and the second counter. A frequency divider comprising means for dividing the frequency into a predetermined number based on the output of the frequency divider.