JPS5951784B2 - programmable divider - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable frequency divider that divides and outputs an input pulse train.

The present invention relates to a programmable frequency divider that divides and outputs pulses, and whose frequency division ratio can be freely changed by external control.

, the object of the present invention is to reduce the duty ratio of the output pulse to approximately 1/
To provide a programmable frequency divider with a frequency of 2.

A conventional programmable frequency divider has a configuration as shown in Fig. 1, and when the desired maximum number of frequency division ratios is M, M≦2.
A 2m counter 1 obtained by cascading a minimum integer m stages of free-flip flop circuits that satisfy ml, a numeral circuit-2 that can set the target frequency division ratio N to the frequency divider in the programmable register, and It consists of a matching circuit 3 which compares the contents of the circuit with the output of the 2m counter and outputs a signal when they match.

Now, the output of the 2m counter increases by 1 every time the input pulse increases by 19.

Eventually, when the content of the dividing ratio numeral circuit 2 and the output of the 2m counter match, the coincidence circuit 3 outputs a coincidence signal.

If the above-mentioned two-effect counter is reset to the zero state based on this proviso, the 2m counter can repeat the zero state and perform program frequency division every time the number of pulses set in the division ratio numeral circuit is input. .

The output signal of the coincidence circuit, that is, the reset signal of the 2m counter, outputs one pulse each time the number of pulses given to the digitization circuit is input to the 2m counter, so this signal can be used as an output. .

There is also another example of a conventional programmable frequency divider having a configuration as shown in FIG.

In other words, a numeral circuit 4 for setting the division ratio N, and a 2m numeral circuit that can set the initial state according to the number placed in the numeral circuit.
It consists of 5 reverse counters.

Now, the 2m reverse counter is first set to N, and each time a pulse to be divided is input, it counts down by 2m, and each time the output of the 2m counter underflows, the number N set in the numeral circuit -4 is reversed by 2m. If it is set in the advance counter, the 2m counter can repeat the same state every time N pulses are input and perform program frequency division.

The alley dart low signal of the 2m counter becomes the output of this frequency divider.

The output waveform obtained in this way has an extremely small duty ratio and cannot often be used as is. Normally, when a pulse output with a duty ratio of 172 is required,
The frequency of the pulse input to the programmable frequency divider was doubled, and the output was further divided in half to extract the desired pulse.

However, with this method, if the frequency of the original oscillation cannot be increased, it becomes extremely difficult to construct the device itself.

The present invention eliminates the drawbacks of the conventional programmable frequency divider and improves the frequency divider so that the frequency of the output waveform is always approximately 1/2.

An example of the configuration is shown in FIG.

□In other words, if the maximum number of N is M, and the minimum integer that satisfies M≦2m is m, then it is constructed with m-1 stages of flip-flops and 2m. "2m/1 counter that can count up to 1" 7, numeric circuit and 2m/1 counter
A matching circuit that returns the output of one counter, 172 minutes
9. Consists of gate circuit-10J waveform shaping circuit-11.

It is now assumed that the frequency dividing ratio N is stored in binary number circuit 6.

Waveform shaping circuit-1:1□ receives the output of matching circuit 28.
This is to reliably reset the m71 counter 7, and a connected monostable multi-bicycle input master-slave flip-flop circuit or the like is used.

The present invention first divides the program frequency by half the throw, and then divides it further by 172, and depending on the evenness or oddness of N, the frequency is divided as follows.

a, N=21 (even number, n is any integer), □In this case, if N is expressed as a binary number, the minimum digit is 0.

In this case, N/2 is equal to the binary number with the smallest digit removed.

(Currently, when the minimum digit of N is 20) Gate circuit-10 returns all input tarok pulses to the counter regardless of the value of the 2° digit of the number digit set in the output Q terminal of flip-flop-9 and the digit circuit. 2m/1 counter 7
, the circuit consisting of the matching circuit 8, the numeral circuit 6, and the waveform shaping circuit 11 is a programmable frequency divider, and its frequency division ratio is as follows: The comparison between the numeral circuit and the 2m71 counter is based on the fact that the lowest digit of N is removed. , that is, since it is performed at N/2, the frequency division ratio is N/2.

(See Figure a) When the output waveform of the waveform shaping circuit 11 is further divided by the 172 frequency divider circuit 9, the input waveform becomes N
It can be done by dividing the frequency.

b, When N=2n+1 (odd number), the minimum digit of N is 1.

At this time, the gate circuit 10 uses the output of the 172 frequency divider 9 to synchronize with the output of the waveform shaping circuit 11 when the output is 1, and transmits the input clock pulse except one to the counter 7, and when the output is 0, it transmits the input clock pulse to the counter 7. Transmit the pulse as is without removing it.

In this way, as shown in FIG. 4, the programmable frequency divider consisting of the 2m71 counter 7, the coincidence circuit 8, and the numeral circuit 6 repeats m frequency division and ゛n+1 frequency division.

If we take this output waveform and divide it by 172 frequency divider -9, we get N
Even if you divide the frequency, the duty is n/(2n+1)
This is approximately 1/2.

FIG. 5 shows another example of the present invention based on a similar idea.

2m/1 reverse counter 18, numeral circuit-19, waveform shaping circuit-20, 172 frequency divider-21, gate circuit-22
Composed of:

The 2m/1 reverse counter 18 performs frequency division by N-1)/2 each time an underflow occurs in each pit except for the smallest digit of the frequency division number N set in the numeral circuit 19.

Similarly to the above, when the minimum digit of the number N placed in the number register circuit 19 is 0, that is, when N is an even number, the gate circuit 22 transmits the input frequency-divided pulse as it is to the counter 18, and when the minimum digit is 1. In other words, when N is an odd number, and if the output of the 172 frequency divider-21 is 1, all but one input pulse to be divided are transmitted, then the number circuit 19, the waveform shaping circuit 20, 2''/゛The programmable frequency divider constituting the counter 18 performs frequency division by (N-1)/2, and then the output of the 172 frequency divider-21 becomes 0, so that the input pulse to be divided is removed. Therefore, frequency division by (N+1)/2 is performed.

That is, when N is an odd number, (N-1)/2, (N+1)
/2 frequency division is repeated alternately.

Furthermore, when N is an even number, the frequency division by N/2 is repeated as described above.

By further dividing the output of the waveform shaping circuit 20 by 172, the frequency can be divided by a duty ratio of 1/2.

FIG. 6a shows the gate circuit 10 of FIG. 3 and the gate circuit 22 of FIG.

The output of the 1/2 frequency divider 9.21 is 2° of the digit circuit 6, 19.
A logical product is performed by the pit line and the gate circuit 23, and the output C thereof is inputted to the D terminal of the flip-flop 25.

FIG. 6C shows a case where the 2° pit is 1, that is, odd number division is performed.

The flip-flop 25 samples the falling pulse of the divided pulse (b) and outputs a Q output as shown in (d).

An output (f) is output by NANDing (NAND 2 6 ) the Q output (d) of the flip-flop 5 and the output (C) of the gate circuit 23 .

In other words, the open frequency-divided pulse (b), which is /l/ in FIG. 6(f), is massed, and the output of the gate 23 (C)
The first shot fired is removed.

Next, the output of the 172 frequency divider is 91. Then, gate 23
Since the output (C) of is O, the output of NAND26 (
f) holds 1. Therefore, the input divided pulse (b)
is not removed.

In this way, the L o. □ alternately increases or decreases the pulse by one shot.

The situation is shown in Fig. 6e, and the gate 23 output 1,
, 0 (game) 24(e) may or may not be removed by one shot.

The gate circuit shown in FIG. 6a is replaced by the gate circuit 10 and
By using the gate circuit 22 in the figure, even in the case of an odd number, the duty ratio of the output of the programmable frequency divider differs only by one pulse of the input divided pulse, and the duty ratio is 1/2. tell.

Needless to say, in the case of an even number, the output will be 1/2 of the Tony-Chi ratio.

As described above, the programmable frequency divider according to the present invention can always output pulses having a duty ratio of approximately 1/2, and does not require any special additional circuit to reduce the linearity to 1/2 after frequency division.

Furthermore, the complexity of the circuit does not increase significantly since only the number of gate circuits is increased.

The present invention can be used in a set in which the oscillation frequency of the original oscillation cannot be increased, and is particularly effective in such a set.

[Brief explanation of the drawing]

Figure 1. 2 is a conventional diagram 3, FIG. 5 is a diagram illustrating a programmable frequency divider circuit according to the present invention, and FIG. 4 is a time diagram explaining the operation of the programmable frequency divider according to the present invention, where a is N. When N is an even number and b is an odd number, FIG. 6a is a circuit diagram of the gate circuit 10 in FIG. 3 and gate circuit 22 in FIG. 5, and b-f are time charts. )1...2m counter, 5...2m reverse counter,
2, 4, 6, 19... Number circuit for setting the division ratio, 3, 8... Matching circuit, 7... 2m/1,
9,21...1/2 frequency divider, 10.22...gate circuit, 11,20...waveform shaping circuit, 18...2m
/1 backward counter.

Claims (1)

[Claims] 1 When M is the maximum value of the frequency division ratio N to be divided, M≦2m, and m is the smallest integer that satisfies /1, then 2m
/1 counter, and a setting means for setting N/4 when N is an even number and (N-1)/2 when N is an odd number, and the above-mentioned 2.
m/) means for comparing the contents of the counter and the number set in the number setting means and detecting a match; a stirring shape shaping means for shaping the signal of the detecting means into a wave shape; a means for resetting the i,1 counter by the output of the waveform shaping means; a means for 1/2 rounding the output of the body shape shaping means; an output from the 1/2q rounding means; The above 2m/1 is determined based on the value of the minimum digit of the set number.
It consists of means for removing two pulses input to the counter.
If N is an even number due to the odd or even number of
A programmable frequency divider, characterized in that the means for removing each of the pulses is operated once at a time. 2 When the frequency division ratio is N, if N is an even number, then N/2. A circuit, a 2m/' reverse counter, and a waveform shaping circuit that converts a signal each time the 2m/1 reverse counter has an un-flow, and the waveform shaping circuit. means for dividing the signal of the circuit by 172; a pulse inputted to the 2m/1 reverse counter based on the output from the means for dividing by 172 and the value of the minimum digit of the number entered in the number setting means; said waveform shaping circuit;
Each time the signal is output, the number set in the numeral circuit is set in the 2m/1 reverse counter, and when N is an even number, the 2m/1 reverse counter is set without operating the means for removing one pulse. A programmable frequency divider, characterized in that the input signal is input to a counter, and when the number is odd, the means for removing one pulse is activated alternately.