JPS6333234U - - Google Patents
Info
- Publication number
- JPS6333234U JPS6333234U JP12619386U JP12619386U JPS6333234U JP S6333234 U JPS6333234 U JP S6333234U JP 12619386 U JP12619386 U JP 12619386U JP 12619386 U JP12619386 U JP 12619386U JP S6333234 U JPS6333234 U JP S6333234U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- data
- pulse signal
- slice
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000008929 regeneration Effects 0.000 claims description 3
- 238000011069 regeneration method Methods 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図は本考案のＦＳＫ信号受信機の回路構成
図、第２図は本考案で使用される伝送信号を示す
図、第３図は第２図で示される信号を送信する送
信側のブロツク図、第４図は有料テレビジヨンシ
ステムを説明するための概略ブロツク図である。
３８……ＦＭ復調回路、３９……レベル検波回
路、４１……制御回路、４３……ローパスフイル
タ回路、４４……第１直流分再生回路、４５……
スライス回路、４６……第２直流分再生回路、Ｔ
Ｒ３……出力トランジスタ。
Figure 1 is a circuit configuration diagram of the FSK signal receiver of the present invention, Figure 2 is a diagram showing the transmission signal used in the present invention, and Figure 3 is a block on the transmitting side that transmits the signal shown in Figure 2. FIG. 4 is a schematic block diagram for explaining a pay television system. 38...FM demodulation circuit, 39...Level detection circuit, 41...Control circuit, 43...Low pass filter circuit, 44...First DC component regeneration circuit, 45...
Slice circuit, 46...Second DC regeneration circuit, T
R3 ...output transistor.
Claims (1)
各データをＦＳＫ変調して送信し、受信機で上記
各データをＦＭ復調して制御回路に供給するとと
もに、レベル検波回路によつて上記無変調部分に
対応したパルス信号を形成し、このパルス信号に
もとづいて前記制御回路がデータの始まりを検出
し、上記各復調データをデコードするようにした
ものにおいて、前記レベル検波回路の出力信号は
ローパスフイルタ回路及び第１直流分再生回路を
介して、一対のトランジスタを差動接続して構成
されるとともにそのスライスレベルが十分高く設
定されたスライス回路に入力され、該スライス回
路の出力を第２直流分再生回路を介して第３トラ
ンジスタに印加し、この第３トランジスタの出力
端から得られるパルス信号を上記制御回路に供給
してなるＦＳＫ信号受信機。 Each piece of data is FSK-modulated and transmitted with the part indicating the division between data unmodulated, and the receiver demodulates each data using FM and supplies it to the control circuit. A pulse signal corresponding to each part is formed, and the control circuit detects the start of data based on this pulse signal and decodes each demodulated data, wherein the output signal of the level detection circuit is passed through a low-pass filter. The output of the slice circuit is inputted via the circuit and the first DC component regeneration circuit to a slice circuit configured by differentially connecting a pair of transistors and whose slice level is set to a sufficiently high level, and the output of the slice circuit is converted into a second DC component. An FSK signal receiver in which a pulse signal is applied to a third transistor via a reproduction circuit and a pulse signal obtained from an output terminal of the third transistor is supplied to the control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12619386U JPS6333234U (en) | 1986-08-19 | 1986-08-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12619386U JPS6333234U (en) | 1986-08-19 | 1986-08-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6333234U true JPS6333234U (en) | 1988-03-03 |
Family
ID=31019765
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12619386U Pending JPS6333234U (en) | 1986-08-19 | 1986-08-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6333234U (en) |
-
1986
- 1986-08-19 JP JP12619386U patent/JPS6333234U/ja active Pending
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