JPS61206334U - - Google Patents
Info
- Publication number
- JPS61206334U JPS61206334U JP1985089598U JP8959885U JPS61206334U JP S61206334 U JPS61206334 U JP S61206334U JP 1985089598 U JP1985089598 U JP 1985089598U JP 8959885 U JP8959885 U JP 8959885U JP S61206334 U JPS61206334 U JP S61206334U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- output
- display control
- mode
- audio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims description 3
- 238000001514 detection method Methods 0.000 claims description 3
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 7
- 238000001228 spectrum Methods 0.000 description 2
Landscapes
- Television Receiver Circuits (AREA)
- Circuits Of Receivers In General (AREA)
- Stereo-Broadcasting Methods (AREA)
Description
第１図はこの考案のモード表示制御回路の実施
例を示すブロツク図、第２図はその音声多重復調
回路を示すブロツク図、第３図はＦＭ検波特性を
示す説明図、第４図はＦＭステレオ放送の周波数
スペクトラムを示す説明図、第５図は音声多重放
送の周波数スペクトラムを示す説明図、第６図は
音声多重放送およびＦＭ放送を受信する放送受信
装置を示すブロツク図、第７図は中間周波増幅回
路の同調特性を示す説明図である。
６…中間周波増幅回路、８…ＦＭ検波回路、１
２…音声多重復調回路、２２…レベル判定手段と
してのＤＣレベル判定回路、２４…表示切換手段
としての表示切換論理回路。
Fig. 1 is a block diagram showing an embodiment of the mode display control circuit of this invention, Fig. 2 is a block diagram showing its audio multiplex demodulation circuit, Fig. 3 is an explanatory diagram showing FM detection characteristics, and Fig. 4 is an FM FIG. 5 is an explanatory diagram showing the frequency spectrum of stereo broadcasting. FIG. 5 is an explanatory diagram showing the frequency spectrum of audio multiplex broadcasting. FIG. 6 is a block diagram showing a broadcast receiving device for receiving audio multiplex broadcasting and FM broadcasting. FIG. 2 is an explanatory diagram showing tuning characteristics of an intermediate frequency amplification circuit. 6...Intermediate frequency amplification circuit, 8...FM detection circuit, 1
2...Audio multiplex demodulation circuit, 22...DC level judgment circuit as level judgment means, 24...Display switching logic circuit as display switching means.
Claims (1)
重副搬送波によつて音声多重復調モードを判別し
て音声多重モードを表わすモード表示信号を出力
するとともに、入力される表示制御信号に応じて
モード表示信号が制御可能にされた音声多重復調
回路と、ＦＭ検波回路の直流出力が特定のレベル
内か否かを判定するレベル判定手段とを備え、前
記音声多重復調回路に前記表示制御信号として前
記レベル判定回路のレベル判定出力を加え、この
レベル判定出力によつて前記モード表示信号を制
御することを特徴とするモード表示制御回路。 (2) 前記音声多重復調回路に、前記レベル判定
出力、中間周波増幅回路の同調出力またはＦＭス
テレオ復調回路の出力を前記表示制御信号として
加える表示切換手段とを設置したことを特徴とす
る実用新案登録請求の範囲第１項に記載のモード
表示制御回路。[Claims for Utility Model Registration] (1) Demodulating the audio multiplex signal, determining the audio multiplexing demodulation mode based on the audio multiplexing subcarrier, and outputting a mode display signal representing the audio multiplexing mode; The audio multiplexing and demodulating circuit includes an audio multiplexing and demodulating circuit in which a mode display signal can be controlled in accordance with a display control signal, and a level determining means for determining whether or not the DC output of the FM detection circuit is within a specific level. A mode display control circuit characterized in that a level determination output of the level determination circuit is added to the display control signal, and the mode display signal is controlled by the level determination output. (2) A utility model characterized in that the audio multiplex demodulation circuit is provided with display switching means for adding the level judgment output, the tuning output of the intermediate frequency amplification circuit, or the output of the FM stereo demodulation circuit as the display control signal. A mode display control circuit according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985089598U JPH0317486Y2 (en) | 1985-06-14 | 1985-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985089598U JPH0317486Y2 (en) | 1985-06-14 | 1985-06-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61206334U true JPS61206334U (en) | 1986-12-26 |
| JPH0317486Y2 JPH0317486Y2 (en) | 1991-04-12 |
Family
ID=30643822
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985089598U Expired JPH0317486Y2 (en) | 1985-06-14 | 1985-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0317486Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067546A (en) * | 2005-08-29 | 2007-03-15 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and sound multiplex signal processing circuit |
-
1985
- 1985-06-14 JP JP1985089598U patent/JPH0317486Y2/ja not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007067546A (en) * | 2005-08-29 | 2007-03-15 | Sanyo Electric Co Ltd | Semiconductor integrated circuit and sound multiplex signal processing circuit |
| JP4700440B2 (en) * | 2005-08-29 | 2011-06-15 | 三洋電機株式会社 | Semiconductor integrated circuit and audio multiplex signal processing circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0317486Y2 (en) | 1991-04-12 |
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