JPH0232256U - - Google Patents
Info
- Publication number
- JPH0232256U JPH0232256U JP11064188U JP11064188U JPH0232256U JP H0232256 U JPH0232256 U JP H0232256U JP 11064188 U JP11064188 U JP 11064188U JP 11064188 U JP11064188 U JP 11064188U JP H0232256 U JPH0232256 U JP H0232256U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- detected signal
- receivers
- level
- detected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
Description
第１図はこの考案の一実施例に係るＦＳＫ変調
方式およびダイバーシチ受信方式を用いたデータ
受信システムの構成を示すブロツク図、第２図は
第１図に示した直流レベルバランス回路の構成を
示すブロツク図、第３図は第２図の回路図、第４
図は従来のＦＳＫ変調方式およびダイバーシチ受
信方式を用いたデータ受信システムの構成を示す
ブロツク図、第５図は符号誤りの発生を説明する
ための図である。
６……第１の受信機、７……第２の受信機、８
……直流レベルバランス回路、９……スペースダ
イバーシチ回路、１０……復調回路、１１……デ
ータ処理装置。
FIG. 1 is a block diagram showing the configuration of a data reception system using the FSK modulation method and diversity reception method according to an embodiment of this invention, and FIG. 2 shows the configuration of the DC level balance circuit shown in FIG. 1. Block diagram, Figure 3 is the circuit diagram of Figure 2, Figure 4
The figure is a block diagram showing the configuration of a data receiving system using the conventional FSK modulation method and diversity reception method, and FIG. 5 is a diagram for explaining the occurrence of code errors. 6...first receiver, 7...second receiver, 8
... DC level balance circuit, 9 ... Space diversity circuit, 10 ... Demodulation circuit, 11 ... Data processing device.
Claims (1)
機からの各検波信号の直流レベルを一定に保つ直
流レベルバランス回路と、この直流レベルバラン
ス回路を介し前記各受信機から得られる各検波信
号から各検波信号の電界強度信号に応じていずれ
か１つの検波信号を選択するスペースダイバーシ
チ回路と、このスペースダイバーシチ回路により
選択された検波信号を復調する復調回路とを具備
するデータ受信システム。 A plurality of receivers that operate independently, a DC level balance circuit that keeps the DC level of each detected signal from these receivers constant, and each detected signal obtained from each of the receivers through this DC level balance circuit. A data receiving system comprising: a space diversity circuit that selects one of the detected signals according to a field strength signal of each detected signal; and a demodulation circuit that demodulates the detected signal selected by the space diversity circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11064188U JPH0232256U (en) | 1988-08-25 | 1988-08-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11064188U JPH0232256U (en) | 1988-08-25 | 1988-08-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0232256U true JPH0232256U (en) | 1990-02-28 |
Family
ID=31347983
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11064188U Pending JPH0232256U (en) | 1988-08-25 | 1988-08-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0232256U (en) |
-
1988
- 1988-08-25 JP JP11064188U patent/JPH0232256U/ja active Pending
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