JPS63318768A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63318768A JPS63318768A JP62154665A JP15466587A JPS63318768A JP S63318768 A JPS63318768 A JP S63318768A JP 62154665 A JP62154665 A JP 62154665A JP 15466587 A JP15466587 A JP 15466587A JP S63318768 A JPS63318768 A JP S63318768A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- groove
- film
- oxidized
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 150000004767 nitrides Chemical class 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000003860 storage Methods 0.000 claims abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 7
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 7
- 239000010703 silicon Substances 0.000 claims abstract description 7
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 10
- 238000002955 isolation Methods 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 2
- 238000005121 nitriding Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 238000000926 separation method Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000012528 membrane Substances 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 1
- HXNZTJULPKRNPR-UHFFFAOYSA-N borinine Chemical compound B1=CC=CC=C1 HXNZTJULPKRNPR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、溝底でセルを分離する構造のダイナミックＲ
ＡＭ（ランダム アクセス メモリ）に関連する半導体
装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dynamic R of a structure that separates cells at the groove bottom.
The present invention relates to a method of manufacturing a semiconductor device related to AM (Random Access Memory).
従来の技術
溝底に、高濃度Ｐ層を設けて、特別に分離用の厚い絶縁
膜を形成することなく、セル間の分離をおこなう方式の
ＤＲＡＭが提案されている（第３図）。Conventional Technology A DRAM has been proposed in which a high concentration P layer is provided at the bottom of the groove to isolate cells without forming a special thick insulating film for isolation (FIG. 3).
第３図において、２ｏはシリコン半導体基板、２１は基
板に形成された溝の内壁及び底部に形成された酸化膜、
２２は溝の底部下の基板内に形成された分離用戸領域、
２３は溝内に形成されたポリシリコンプレート、２４は
溝の内壁に形成されたストレージ用ｎ 領域である。領
域２４とプレート２３間で蓄積容量が形成されている。In FIG. 3, 2o is a silicon semiconductor substrate, 21 is an oxide film formed on the inner wall and bottom of a groove formed in the substrate,
22 is a separation door area formed in the substrate under the bottom of the groove;
23 is a polysilicon plate formed in the trench, and 24 is a storage n-region formed on the inner wall of the trench. A storage capacitor is formed between the region 24 and the plate 23.
２６は表面の厚い絶縁膜、２７は書込み、読出し用のＭ
ＯＳ）ランジスタのドレイン領域で領域１３とつながっ
ている。２６はＭＯＳ）ランジスタのポリシリコンゲー
トである。又、溝容量の耐圧向上のため、薄い酸化膜の
上に窒化膜を堆積し、さらにこの窒化膜の上層を酸化し
た３層構造が用いられる。26 is a thick insulating film on the surface, 27 is M for writing and reading.
OS) is connected to region 13 at the drain region of the transistor. 26 is a polysilicon gate of a MOS transistor. Further, in order to improve the withstand voltage of the trench capacitance, a three-layer structure is used in which a nitride film is deposited on a thin oxide film, and the upper layer of this nitride film is further oxidized.
発明が解決しようとする問題点
しかし、前記の分離構造を持つＤＲＡＭに、前記の３層
膜を使用した場合、この３層膜の持つ、電圧ストレス下
でのフラットバンドシフトが大きいという特性が、セル
分離を悪化させてしまう。Problems to be Solved by the Invention However, when the above-mentioned three-layer film is used in a DRAM having the above-mentioned separation structure, the property of this three-layer film that the flat band shift is large under voltage stress is This will worsen cell separation.
さらに、前記分離構造は、薄い絶縁膜が溝底で破壊して
いる場合、全ビア）不良を招く。本発明は、このような
従来の問題を解決し、極めて簡単な工程で、前記分離構
造に、前記３層膜を適用可能とし、さらに、全ビット不
良を招く溝底での薄い絶縁膜の破壊を防ぐものである。Furthermore, the isolation structure may lead to failure of all vias if the thin insulating film is destroyed at the bottom of the trench. The present invention solves these conventional problems, makes it possible to apply the three-layer film to the isolation structure with an extremely simple process, and furthermore prevents the destruction of the thin insulating film at the bottom of the groove, which would lead to all bit defects. This is to prevent
問題点を解決するための手段
本発明の半導体装置の製造方法は、溝の堀られたシリコ
ン基板を熱酸化する工程と、その後窒化膜を堆積する工
程と、たとえば異方性のエツチングにより溝側壁を残し
て、水平部（底部）の前記窒化膜を除去する工程と、前
記窒化膜表面を酸化しかつ前記窒化膜を除去した部分の
基板を同時に酸化する工程を備えたものであり、このよ
うにしてできた側壁の３層膜をＤＲＡＭのストレージ容
量の絶縁膜として用いるもので、側壁には耐圧特性のよ
い３層絶縁膜を作り、同時に溝底には、厚い酸化膜を形
成することを特徴とする。Means for Solving the Problems The method of manufacturing a semiconductor device of the present invention includes a step of thermally oxidizing a silicon substrate in which a trench has been dug, a step of depositing a nitride film after that, and etching the trench sidewalls by, for example, anisotropic etching. The method includes a step of removing the nitride film in the horizontal part (bottom) while leaving the nitride film, and a step of simultaneously oxidizing the surface of the nitride film and the part of the substrate from which the nitride film has been removed. The three-layer film on the sidewalls formed by the process is used as an insulating film for the storage capacity of DRAM.A three-layer insulating film with good voltage resistance characteristics is formed on the sidewalls, and at the same time, a thick oxide film is formed at the bottom of the trench. Features.
作 用
本発明は上記構成により、次のような作用が発揮される
。Effects The present invention exhibits the following effects due to the above configuration.
■ ＤＲＡＭのストレージ容量となる側壁部には、耐圧
特性が良い、充分薄い３層（酸化膜／窒化膜／酸化膜）
膜が形成される。■ The sidewalls, which serve as the storage capacity of DRAM, have three sufficiently thin layers (oxide film/nitride film/oxide film) with good voltage resistance characteristics.
A film is formed.
■ 溝底には、比較的厚い酸化膜が形成され、全ビット
不良の原因となる溝底での薄い絶縁膜の耐圧不良を防ぐ
。■ A relatively thick oxide film is formed at the bottom of the trench to prevent breakdown voltage failure of the thin insulating film at the bottom of the trench, which causes all bit failures.
■ ■、■がマスク工程なしで、異方性エツチングする
だけで同時に形成さ−れる。2) 2) and 2) can be formed simultaneously by just anisotropic etching without a mask process.
■ 溝底に高濃度Ｐ層を設けて、溝底でセルを分離する
方式のＤＲＡＭのセルの溝底分離部の寄生トランジスタ
のＶ７を高くする。(2) A high-concentration P layer is provided at the trench bottom to increase the V7 of the parasitic transistor in the trench bottom isolation portion of a DRAM cell that isolates cells at the trench bottom.
■、■の分離構造で、３層膜の使用を可能にする。The separation structure of ■ and ■ enables the use of three-layer membranes.
実施例
第２図に本発明の一実施例方法により形成されたＤＲＡ
Ｍ容量部および分離部の構造を示す。１はＳｔ（シリコ
ン）半導体基板、２，４．５は酸化膜で、酸化膜２は窒
化膜３の表面に形成されたもので、４は基板の溝の側壁
に形成され、５は基板の溝底部に形成されたものである
。６は溝内に埋込まれたポリシリコンプレートである。Embodiment FIG. 2 shows a DRA formed by an embodiment method of the present invention.
The structure of the M capacitor section and separation section is shown. 1 is an St (silicon) semiconductor substrate, 2 and 4.5 are oxide films, the oxide film 2 is formed on the surface of the nitride film 3, 4 is formed on the side wall of the groove of the substrate, and 5 is the oxide film formed on the surface of the nitride film 3. It is formed at the bottom of the groove. 6 is a polysilicon plate embedded in the groove.
７は基板の溝側壁に形成されたストレージノードｎ＋領
域、８は分離用のＰ＋領域である。Reference numeral 7 indicates a storage node n+ region formed on the trench sidewall of the substrate, and reference numeral 8 indicates a P+ region for isolation.
第１図に本発明の製造方法を実施したＤＲＡＭ容量の分
離部の製造工程を示す。まず、溝１ｏの堀られたシリコ
ン半導体基板１を熱酸化し１０ｎｍ以下の酸化膜４を得
るａｏこのとき戸領域８は形成されている。７は溝１０
０基板内壁に形成されたストレージノードｎ＋領域であ
る。さらにｂ図に示すようにシリコン窒化膜３を２０ｎ
ｍ以下ＣＶＤ法にて堆積する。次に異方性エッチで、水
平部分、すなわち溝底部の窒化膜３の一部を除去し、Ｃ
に示すような状態にする。なお、領域８はａ等の他の工
程で形成してもよい。この状態から窒化膜３の上層表面
を酸化を行うと、窒化膜３が酸化されるよりも、はるか
に速いレート、で基板が酸化されるので、ｄのように窒
化膜３の表面に薄い酸化膜２と比較的厚い酸化膜６が溝
底に形成され、信頼性の高い確実な分離が可能となる。FIG. 1 shows the manufacturing process of a DRAM capacity separation section using the manufacturing method of the present invention. First, a silicon semiconductor substrate 1 in which a groove 1o has been dug is thermally oxidized to obtain an oxide film 4 having a thickness of 10 nm or less.At this time, a door region 8 is formed. 7 is groove 10
This is a storage node n+ region formed on the inner wall of the 0 substrate. Furthermore, as shown in figure b, a silicon nitride film 3 of 20nm was added.
The thickness is deposited using the CVD method. Next, a part of the nitride film 3 at the horizontal part, that is, at the bottom of the groove is removed by anisotropic etching.
Make the condition as shown. Note that the region 8 may be formed in other steps such as a. If the upper surface of the nitride film 3 is oxidized from this state, the substrate will be oxidized at a much faster rate than the nitride film 3. A film 2 and a relatively thick oxide film 6 are formed at the bottom of the trench, allowing reliable and reliable isolation.
なお、酸化膜４は１０ｎｍ以下、窒化膜３は２００ｎｍ
ａ以下とすることが、ＤＲＡＭの蓄積容量の点か
らは望ましい。こうしたのち、溝１０にポリシリコンプ
レート６、表面の絶縁膜、ＭＯＳ）ランジスタを形成し
て第２図の構造を得る。Note that the oxide film 4 has a thickness of 10 nm or less, and the nitride film 3 has a thickness of 200 nm.
From the viewpoint of the storage capacity of the DRAM, it is desirable that the value be equal to or less than a. After this, a polysilicon plate 6, an insulating film on the surface, and a MOS transistor are formed in the trench 10 to obtain the structure shown in FIG.
発明の効果
本発明に基づいて製造されるＤＲＡＭのストレージ容量
部分は、従来に比べ、
■ 全ビット不良を招く、溝底での絶縁不良が解消され
る。Effects of the Invention Compared to the conventional storage capacity portion of a DRAM manufactured according to the present invention, (1) Insulation defects at the bottom of the trench, which lead to all bit defects, are eliminated.
■ ０ＮＯ（酸化膜−窒化膜一酸化膜）三層絶縁膜のも
つ、良い耐圧／経時破壊特性が、第３図の構造につけ加
わる。本発明がなければ、ＯＮＯ膜はストレス下でのフ
ラットバンドシフトが大きく、第３図の構造でのセル分
離の信頼性が得られない。(2) The structure shown in FIG. 3 is further enhanced by the excellent breakdown voltage/time-dependent breakdown characteristics of the 0NO (oxide film, nitride film, and monoxide film) three-layer insulating film. Without the present invention, the ONO membrane would have a large flat band shift under stress, and the reliability of cell isolation in the structure of FIG. 3 would not be achieved.
の点で優れたものとなる。そして、本発明はマスク工程
のない簡単な工程で上記構造を実現でき、超高密度なり
ＲＡＭの実現に大きく寄与するものである。It is excellent in terms of. The present invention can realize the above structure through a simple process without a mask process, and greatly contributes to the realization of ultra-high density RAM.
第１図は本発明の一実施例方法におけるＤＲＡＭ容量・
分離の製造工程を示す断面図、第２図は本実施例方法に
て形成された同容量・分離部の断面図、第３図は従来の
容量・分離部、の断面図である。
１・・・・・・８１ 基板、２，４，５・・・・・・
酸化膜、３・・・・・・窒化膜、１０・・・・・・溝。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図 １０−溝
ωＪ
（ｂ）
第１図 （Ｃ）
ｌθ
（Ｏ乙ン
１−−−ＳＬ基板
Ｚ、４． Ｓ−−一酸化膜
３−変化膜
６−°ボリンリボンプレート
７− ストレージ ノードｎ？領域
δ−分離量Ｐ＋領域
嬉２図FIG. 1 shows the DRAM capacity and
FIG. 2 is a cross-sectional view of the same capacitor/separator formed by the method of this embodiment, and FIG. 3 is a cross-sectional view of a conventional capacitor/separator. 1...81 Board, 2, 4, 5...
Oxide film, 3... Nitride film, 10... Groove. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 10 - Groove ωJ (b) Figure 1 (C) lθ (O 1 - SL substrate Z, 4. S - Monoxide film 3 - Variable film 6 - ° Borin ribbon plate 7 - Storage node n ?Area δ - Separation amount P + Area happiness 2 figure
Claims (1)
を酸化し、その上に窒化膜を堆積した後、前記側壁の窒
化膜を残したまま前記溝底の窒化膜を除去し、前記窒化
膜表面ならびに前記窒化膜を除去した部分を酸化するこ
とにより、ダイナミックＲＡＭのストレージ容量部分を
形成する半導体装置の製造方法。After oxidizing the trench sidewalls and bottom of the trench-filled silicon substrate and depositing a nitride film thereon, the nitride film at the trench bottom is removed while leaving the nitride film on the sidewalls, and the nitride film is removed. A method of manufacturing a semiconductor device in which a storage capacitor portion of a dynamic RAM is formed by oxidizing the surface and the portion from which the nitride film has been removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62154665A JPS63318768A (en) | 1987-06-22 | 1987-06-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62154665A JPS63318768A (en) | 1987-06-22 | 1987-06-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63318768A true JPS63318768A (en) | 1988-12-27 |
Family
ID=15589214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62154665A Pending JPS63318768A (en) | 1987-06-22 | 1987-06-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63318768A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
-
1987
- 1987-06-22 JP JP62154665A patent/JPS63318768A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6469345B2 (en) | 2000-01-14 | 2002-10-22 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US6864532B2 (en) | 2000-01-14 | 2005-03-08 | Denso Corporation | Semiconductor device and method for manufacturing the same |
| US7354829B2 (en) | 2000-01-14 | 2008-04-08 | Denso Corporation | Trench-gate transistor with ono gate dielectric and fabrication process therefor |
| DE10101568B4 (en) * | 2000-01-14 | 2011-04-07 | DENSO CORPORATION, Kariya-shi | Semiconductor device and method of making the same |
| US6521538B2 (en) | 2000-02-28 | 2003-02-18 | Denso Corporation | Method of forming a trench with a rounded bottom in a semiconductor device |
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