JPS63314601A - Interruption controller for computer - Google Patents

Abstract

PURPOSE:To prevent a foul interruption caused by a manual resetting action in an interruption inhibiting state of a main controller, by adding a signal holding circuit to an interruption request signal output circuit of a secondary controller to hold the output of an interruption request invalidating signal when an interruption inhibiting signal is received from a CPU of a main controller. CONSTITUTION:An interruption signal output circuit 6 is added to the secondary controller 2 together with a signal holding circuit 15 which holds the output of an interruption request invalidating signal to the circuit 6 when an interruption inhibiting signal is supplied from a CPU 3 of a main controller 1. Then the circuit 6 is activated as long as the controller 1 is kept under an interruption valid state. Thus the interruption request given from the controller 2 is validated and the circuit 6 is set under an inactive state with an interruption inhibiting state. Thus the interruption request is invalidated.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a multi-computer type control device consisting of a main control device each having a computer and a sub-control device under the control of the main control device, and particularly to a sub-control device. This relates to initial interrupt control from the control device to the computer of the main control device.

(Prior Art) FIG. 3 is a block diagram of an interrupt control device for implementing a conventional interrupt control method.

In the figure, (1) is the main controller, (2) is the sub-controller, (3) is the CPU provided in the main controller (1), (4) is the CPU provided in the sub-controller (2), and (5) is the CPU provided in the sub-controller (2). 2”) (7) CPU (3)
, (4) is a two-board memory accessible from (4), (6) is a D-type flip-flop (F-F), (7) is an interrupt circuit, (8) is a reset circuit selected by the main controller (1), ( 9) is a reset circuit provided in the sub-controller (2), and (10) is a reset circuit provided in the main controller (1).
) reset SW, (11) is the subcontroller (
2) is the reset SW. (12) is the reset circuit (
(13) is an OR circuit that ORs the interrupt signal output by the CPU (9) and the interrupt signal output by the CPU (4);
) is an OR circuit that logically sums the interrupt signals output by the circuits.

(14) is a slot prepared by the main controller to attach a sub-controller.

Figures 4(a) to (b) show subcontrollers (2-1) to (2-31) inserted in various arrangement orders into slots (14-1) to (14-3) of the main controller (1). FIG.

FIG. 5 is a flowchart showing processing related to interrupt prohibition.

Figure 6 shows the input terminals CK, D and output terminals Q of the D-type F-F.
The timing chart of Φ is shown, and the state of the terminal when the terminal CK rises is output to Q, and its negation is output to Φ.

Next, the operation will be explained. Main controller (1)
As shown in Figure 4, the sub controllers (2-1) to (2
-3) can be inserted into any slots (14-1) to (14-3).

When the CPU (3) is initially started for some reason, the processing shown in the flowchart of FIG. 5 is executed. First, check what kind of sub-controllers (2-1) to (2-3) are inserted into each slot (14-1) to (14-3) of the main controller (1) (5-1). ). Next, interrupt masks corresponding to each one are applied (5-2), and then the main controller (1) executes initial processing (5-3).
1) resets the interrupt mask (5-4) L. The following processes are executed in sequence.

When disabling interrupts here, it is necessary to check the set states of the subcontrollers (2-1) to (2-3) in order to set the interrupt mask, and then to reset the interrupt mask. Therefore, in the conventional interrupt control method, in order to eliminate this complicated procedure, an interrupt permission flag is provided in the two-board memory (5) to control the interrupt request of the sub-controller (2).

For example, in FIG. 3, when the CPU (4) attempts to generate an interrupt request, the CPU (4) checks the interrupt enable flag provided in the 2-board memory (5), and if it is in the enabled state, the 6th interrupt request is issued. As shown in the time chart in the figure,
The clock signal of "H" level is output to the D type F-F (6) via the OR circuit (12).As a result, the D type F
-F From the Q terminal of (6), connect the main controller (1)
An interrupt request signal is output to the interrupt circuit (7) of the CP.
An interrupt request is made to U (3) (route ■). On the other hand, when the interrupt enable flag of the 2-vote memory is in the disabled state, the CPU (4) waits for generation of an interrupt request until it becomes enabled, or cancels it.

In addition, when requesting an interrupt to the CPU (3) using a hardware mechanism manually operated on the sub-controller (2) side, turn on the reset SW (11) connected to the reset circuit (9). A level clock signal is output from the reset circuit (9) to the CPU (4) via the OR circuit (13) to reset the CPU (4), while the clock signal is output via the OR circuit (12). is output to the D-type F-F (6), and from the Q terminal, an interrupt request signal to the CPU (3) is output in the same manner as above (route ■).

As described above, after receiving an interrupt request from the sub-controller (2), the CPU (3) completes the interrupt handling process and sends a clear signal to the D-type F-F via path (■).
(6) to the CLR terminal to clear the D type FF (6) and reset the interrupt signal latched by the corresponding type FF (6).

Or, for some reason, the main controller (1
) and the sub-controller (2), by turning on the reset SW (10), a reset signal is manually sent to the CPU (3) and CPU (4) through the routes of ■ and ■, and the main controller (1) is reset. , subcontroller (
2) becomes the initial state.

(Problems to be Solved by the Invention) Conventionally, interrupts between the main controller (1) and the sub-controller (2) are controlled by the interrupt permission flag in the 2-board memory (5).However, the sub-controller (2) An interrupt request made by manually resetting the H/W of the sub-controller (2) is manually input to the main controller (1) without checking the interrupt permission flag. In order to prevent unauthorized interrupts caused by resets, it was necessary to set interrupt masks using complicated procedures.

The present invention was made to solve the above-mentioned problems, and aims to provide a device with a simple configuration that prevents unauthorized interrupts caused by H/W reset when the main controller (1) is in an interrupt-disabled state.

(Means for Solving the Problems) The computer interrupt control device according to the present invention, when receiving an interrupt disable signal from the central processing unit of the main control device, sends the interrupt request signal output circuit provided in the sub control device to the interrupt request signal output circuit provided in the sub control device. A signal holding circuit for outputting and holding an interrupt request invalidation signal is provided in the sub-control device.

(Operation) According to the present invention, when an interrupt disable signal is manually input from the interrupt request signal output circuit to the sub-control device and the central processing unit of the main control device, an interrupt request disable signal is output to the interrupt request signal output circuit. By having a signal holding circuit that holds the signal, if the main controller is in the interrupt enabled state, the interrupt request signal output circuit is activated and the interrupt request from the sub controller is enabled, and if the interrupt is disabled, the interrupt request is output. The signal output circuit is made inactive to invalidate the interrupt request.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention, and (1
) to (13) are completely the same as the conventional device.

(15) is a D-type F-F which is a means for making the D-type F-F (6) controllable by the main controller (1).

The operations of the main controller (1) and sub-controller (2) with the above configuration will be explained along the flowchart of FIG. 2.

'First, turn on the power to the main controller (1) or turn on the reset SW (10) and turn on the CPU (
When a reset signal is input to 3), the reset circuit (8)
At the same time that a clear signal is output from the D-type F-F (15), the CPU (3) clears the D-type F-F (6) (2-1). The D type F-F (15) has the D terminal pulled up, so the CK from CPU (3)
If an ON signal is sent to the terminal, the Q terminal will immediately send an ON signal. On the other hand, since the D terminal of the one-way type F -F (6) is connected to the Q terminal of the D type F -F (15), the D type F -F (
6) is in the OFF state. Therefore, D type F-F (
Even if the CK terminal of 6) is turned ON, the Q terminal does not turn ON.

Next, the CPU (3) sets the interrupt enable flag provided on the 2-board memory to an interrupt disabled state (2-
2) Execute initial processing (2-3). The main controller (1) remains in an interrupt-disabled state until this processing is completed. Here, even if the CPU (4) tries to generate an interrupt request, the interrupt enable flag on the 2-port memory (5) is in the interrupt disabled state, so the interrupt is disabled. In addition, even if the reset 5W (11) is turned on and the CK terminal of the D type F - F (6) is turned on via route ■, the
Type F -F (6) is in the OFF state, so the Q terminal is ONL.
As a result, interrupts caused by H/W reset are disabled.

After the initial processing has been completed, the CPU (3) sets the interrupt enable flag and the CK terminal of the D-type F-F (15) to set the interrupt enable<2-4) and (2-5). Since the D terminal of this backward type F・F (Is) is ON, the D type F
-F (6) D terminal is turned on and D type F -F (6
) becomes ON, and the main controller (1) becomes interrupt enabled. After this, the CPU (4) confirms that the interrupt permission flag is interrupt permission, and can generate an interrupt via path (3). Also, reset SW (11
) can be input to the CPU (3) via path (3).

Although the above embodiment describes an example in which only one sub-controller (2) is provided, it goes without saying that even if multiple sub-controllers are provided, the same operation is possible and the same effects as in the above embodiment can be obtained. .

Further, if the D-type F-F (6) and (14) can operate in the same way with other latch circuits, it goes without saying that the same effects as in the above embodiment can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, when the main control device is in an interrupt disabled state such as when executing initial processing, unauthorized interrupts from the sub control device can be prevented by simply adding a single signal holding circuit. Therefore, there is no need to set or reset an interrupt mask, which burdens the central processing unit on the main controller side, and an inexpensive interrupt control device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a computer interrupt control device according to an embodiment of the present invention, FIG. 2 is a flowchart of initial processing of a main controller according to an embodiment of the present invention, and FIG. 3 is a diagram of a conventional interrupt control device. The configuration diagram, Figures 4(a) to (C) are connection examples of the main controller and sub-controller, Figure 5 is a flowchart related to interrupt prohibition of the conventional main controller, and Figure 6 is a D-type F-F.
The timing chart is shown below. In the figure, (1) is the main controller, (2) is the sub-controller, and (3) and (4) are the CPUs. (6), (15) D type F-F. (7) is an interrupt circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] In a multi-computer type control device in which the main control device and the sub-control device each include a central processing unit and mutual processing of control data is performed between the central processing units, the sub-control device has an interrupt permission flag on the main control device side. An interrupt request signal output from the central processing unit based on reading,
Or an interrupt request signal output circuit that outputs an interrupt request signal outputted from the interrupt signal circuit at any time by manual operation to the central processing unit on the main controller side, and an interrupt disable signal outputted from the central processing unit of the main controller when inputting the interrupt request signal. , and a signal holding circuit for outputting and holding an interrupt request invalidation signal to the interrupt request signal output circuit.