JPH02130660A - Writing protection circuit - Google Patents

Abstract

PURPOSE:To prevent an unauthorized access by providing a comparator which compares a port identification code and outputs a matching signal, and a means to output a gate enable signal which permits the output of port data to a gate circuit. CONSTITUTION:In a comparator 11, the port ID of data inputted from a port ID line J and a data line A are compared. Then, when the port ID is coincident, a matching signal D is outputted. When the signal D is active, a timing signal E rises up and the signal E is latched by an enable latching circuit 12. After that, an enable signal F is made active. When the latch of the signal F is finished, the data is transmitted from a CPU. Here, an enable generating circuit 13 executes an OR arithmetic processing from the signal F and a port selecting signal G and outputs a gate enable signal H. Accordingly, a data gate circuit 10 is opened and the data outputted from an access side is sent through a port data line B to an I/O port.

Description

[Detailed Description of the Invention] [Objective of the Invention] [Industrial Application Field] The present invention provides a method for accessing a port from another system, module, or a processor within a module to obtain data for executing a desired operation. The present invention relates to a write protection circuit used in writing, and particularly to a write protection circuit that prevents data write malfunctions due to runaway of a preceding system, processor, etc.

[Conventional technology]

Generally, data input/output between systems or within a single module is performed via the I10 port. In other words, if you want to store data in a human-powered port for a long time, for example, select the input port of the other system on the accessing side, such as a processor, and input the data sent from the processor, etc. to the specified address of the selected human-powered port. and the system performs the desired operation. When inputting and outputting data through the I10 port in this manner, it is necessary to input predetermined data (normal data) to a predetermined address of the selected I10 port. This means that the data output from the processor etc.
It is used to make the system perform the desired operation.
This is because if predetermined data is not accurately input to the specified address, the system will perform an unplanned operation, which will have a negative impact on the system.

Conventionally, in order to accurately input predetermined data to the specified address of the selected I10 port, as shown in Figure 3, data is sent to the data line A that sends out the pig output from the access side and to the I10 port. A data gate circuit 1 is provided between the port data line B and the opening/closing of the data gate circuit 1 is controlled by a gate enable signal F output from a comparator circuit 2. This comparison circuit 2 compares the address data actually output from the access side and input through the address line AL with the address data for port designation input manually from the access side through the port address line PL, and compares them with each other. When the port select signal M for selecting the I10 port is input from the access side when the address data of the ports match, the gate enable signal F is output.

- On the other hand, when the gate enable signal F is input from the comparator circuit 2, the data gate circuit 1 opens the gate and sends the data sent from the data line A to the port I10 via the port data line B.

By the way, in the above-described I10 port selection means, if the access side, such as a processor, goes out of control and the address data on the address line AL is disturbed, accurate address data will no longer be input to the comparator circuit 2. Therefore, if the comparator circuit 2 compares with incorrect data and as a result the gate enable signal F is output, or if the port select signal M is input regardless of the address comparison result in the comparator circuit 2, When the gate enable signal F is output from the comparator circuit 2,
Abnormal data is sent to the I10 port.

[Problem to be solved by the invention]

Therefore, in the above circuit, even if the processor on the access side goes out of control and abnormal data is output, it is not possible to prevent input to the I10 port, and for example, the 10 port may affect the entire system or module. If such a control signal is generated, there is a problem that the system or module may malfunction.

The present invention has been made to eliminate the above problems, and is a write method that can prevent unauthorized access to the I10 port due to a runaway processor on the access side or a software bug, and can also protect multiple ports. The purpose is to provide a protection circuit.

[Structure of the Invention] [Means for Solving the Problems] Therefore, in order to achieve the above problems, the present invention provides a gate circuit that controls the passage of port data sent from the access side to the port, and a gate circuit that controls the passage of port data sent from the access side to the port. The identification code of the input/output port is compared with the identification code indicating the destination of the port data actually output from the access side, and when both codes match, a match signal is output that determines the identification code of the human output port to be accessed. and a gate enable that latches the match signal output from this comparison circuit at a predetermined timing and allows the port data to be output to the input/output port upon receiving the port select signal sent from the access side. and data permission means for outputting a signal to the gate circuit.

[Effect]

Therefore, in the present invention, by taking the above measures, when port data is output from the access side to the human output port, the comparison circuit compares the port identification code of the port data actually transmitted and the port specified by the access side. The identification code is compared, a match signal is output according to the comparison result, the output match signal is taken in by the data permission means at a predetermined timing, and the data permission means is sent to the port output from the access side. When the select signal is received, a gate enable signal is generated, and when the gate enable signal is output from the data permitting means, the gate circuit is opened and the data output from the access side is sent to the input/output port.

〔Example〕

Next, a write protection circuit which is an embodiment of the present invention will be described with reference to FIGS. 1 and 2. This write protection circuit consists of a data gate circuit 10 that passes or blocks data output from the processor, etc. on the access side to the I10 port, and a data gate circuit 10 that passes or blocks data output from the access side processor, etc.
D (identification code); an enable latch circuit 12 that latches the port ID data determined by the comparison circuit 11 and outputs an enable signal to permit data transmission to the I10 bottom; and this enable latch circuit. 12 and a port select signal sent from the access side, the enable generation circuit 13 outputs a gate enable signal that becomes an opening/closing control signal for the data gate circuit 10. Note that the enable latch circuit 12 and the enable generation circuit 13 constitute data permitting means for permitting data to be sent to the I10 port.

In the data gate circuit 10, a data line A for transmitting data output from the access side is connected to the input terminal side, a port data line B for transmitting port data to the I10 port is connected to the output side terminal, and the enable generation is performed. A gate enable signal, which is an output signal of the circuit 13, is inverted and input as a control signal. The comparison circuit 11 is connected to one end of the data line A connected to the data gate circuit 10 and a port ID line J that transmits port ID data specified on the access side, and is connected to one end of the data line A connected to the data gate circuit 10 and a port ID line J that transmits port ID data specified on the access side. The data output to A is compared with the port ID. In addition, an inverted port ID select signal C indicating that the data output from the access side to the data line A is valid is input to the comparison circuit 11 according to the comparison result of the port ID, and a match signal is accordingly input. Output. The enable latch circuit 12 is composed of a flip-flop circuit, and the comparison circuit 1
The match signal output from 1 is latched at the rising edge of timing signal E, and enable signal F is output. The enable generation circuit 13 uses an OR circuit or the like that performs a logical sum operation.

Next, the operation of the write protection circuit configured as described above will be explained. Note that a case where the CPU accesses the I10 port as the processor on the access side will be described. In such a case, data output from the CPU is input to the comparator circuit 11 through data line A, and port ID data designated by the CPU is input through port ID line J. In this comparison circuit 11, when the port ID select signal C is at a low level, the port IDs of the data input from the port ID line J and the data line A are compared. As a result of the comparison, if the baud 1-ID match, the comparison circuit 11 outputs an active (high level) match signal. Here, the timing signal E is CP
Assuming that the write signal is output from U, the timing signal E rises when the match signal is active, so
It is latched by the enable latch circuit 12, and the enable signal F becomes active (low level). Port ID comparison in comparison circuit 11 and enable latch circuit 12
When the latch of the enable signal F at CP is completed, CP
Data is sent from U to I10 port. At this time, the port select signal G output from the CPU becomes active (low level). Here, the enable generation circuit 13 generates an active (low level) enable signal F.
and the active (low level) port select signal G (because F, G, and H are negative logic signals), and outputs the active (low level) gate enable signal H. Therefore, the data gate circuit 10 is opened and data 1 output from the access side is sent to the I10 port via the port data line B.

Here, if the I10 port is accessed without comparing the port IDs in the comparison circuit 11, the enable signal F is kept inactive (high level), and therefore the gate enable signal H is also inactive (high level).
The state will be maintained, and the data gate circuit 10 will not be opened.

As a result, data for which ID is not specified is I1.
0 port is not sent. Furthermore, even if the port IDs match and the match signal becomes active as a result of comparing the port IDs in the comparison circuit 11, if the I10 port is not accessed and the port select signal G does not become active, the gate enable is activated. Signal H is not active and data gate circuit 10 is not opened.

According to this embodiment, when accessing the I10 port, the port ID of the data output from the access side is
is determined by the comparison circuit 11, and the enable latch circuit 1
2 and the enable generation circuit 13 selects the I10 port and outputs a gate enable signal H that permits access, thereby opening the data gate circuit 10. Therefore, there is no possibility of unauthorized access to the I10 port due to processor runaway or software bugs. Access can be reliably prevented, and therefore malfunctions of systems etc. in which data is input/output via the I10 port can be reliably prevented. In addition, since a baud ID is defined, multiple I10 ports can be protected.

[Effects of the Invention] As described in detail above, according to the present invention, the I1
It is possible to provide a write protection circuit that can prevent unauthorized access to the 0 port and protect a plurality of ports.

[Brief explanation of the drawing]

1 and 2 are diagrams showing one embodiment of the present invention, in which FIG. 1 is a block diagram of a write protection circuit, FIG. 2 is a timing chart, and FIG. 3 is a conventional write protection circuit. It is a block diagram of a circuit. 10...Data gate circuit, 11...Comparison circuit,]
2... Enable latch circuit, 13... Enable generation circuit. Applicant's agent Patent attorney Takehiko Suzue Figure 1, Ward 3, Figure 2

Claims (1)

[Claims] Compare the gate circuit that controls the passage of port data sent from the access side to the port, the identification code of the input/output port specified by the access side, and the identification code that indicates the destination of the port data actually output from the access side. When both codes match, there is a comparison circuit that outputs a match signal that determines the identification code of the input/output port to be accessed, and a comparison circuit that latches the match signal output from this comparison circuit at a predetermined timing and sends it from the access side. 1. A write protection circuit comprising: data permission means for outputting a gate enable signal to the gate circuit to permit output of the port data to the input/output port upon receiving a port select signal.