JPS63313363A - Digital signal processor - Google Patents

Abstract

PURPOSE:To facilitate a system control at the time of edition, etc., by setting a delayed amt. of data in an encoder and a decoder to be the multiple of integer of the length of a block blocked at the time of forming a transmission signal by the encoder. CONSTITUTION:Digital data DI supplied to a 1st input terminal 11 are coded for error correction by the encoder 13 and also blocked at every plural words to form a pseudo video signal VPO. The signal VPO is recorded to a VTR 20. A pseudo video signal VPI regenerated from the VTR 20 is supplied to the decoder 14 and decoded for error correction to be outputted as digital data DO. Now, the delayed amt. of the data in the encoder 13 and the decoder 14 is set up so as to set the sum of the delayed amt. of the same words being included in the data DI and the signal VPO and the delayed amt. of the same words being included in the signal VPI and data DO to be the multiple of integer of the block length blocked at the tie of recording. By this method, the system control at the time of edition, etc., can be facilitated.

Description

[Detailed description of the invention] Hereinafter, the present invention will be explained in the following order.

A. Field of industrial application B1 Overview of the invention C0 Prior art 0 Problems to be solved by the invention E6 Means for solving the problems F0 Effects G. Example G-1. Digital signal recording and reproducing system ( Figure 2) G-λ signal format (Figures 3 to 8) G-3, encoder (Figure 9) G-4, decoder (Figures 10 and 1) G-5, dubbing (Figure 1) (Figure 11) H0 Effect A of the Invention, Industrial Application Field The present invention relates to a digital signal processing device used, for example, when creating a master disc of a compact disc.

B0 Summary of the Invention The present invention provides, in a digital signal processing device used, for example, when creating a master disc for a compact disc, the amount of data delay in an encoder and decoder is reduced to an integral multiple of the block length of the blocking process when forming a transmission signal in the encoder. This allows the system to be easily controlled during editing, etc.

C0 Conventional Technology The cutting process used to create master discs for compact discs (CDs), which are now becoming popular, is usually performed using a digital signal recording and reproducing system consisting of a digital signal processing device (so-called PCM processor) and a VTR (video tape recorder). This is done by supplying the generated digital data to an optical cutting device. In the above-mentioned digital signal recording and reproducing system, during recording, input data is added with an error detection/correction code, interleaved, and then recorded on a magnetic tape in the form of an 1I video signal. Also, during playback, data is extracted from the pseudo video signal played from the magnetic tape,
After processing such as de-interleaving and error correction/correction is performed on this data, it is output as output data. Regarding such a digital signal recording and reproducing system, for example, Japanese Patent Laid-Open No. 58-48279~
A device as described in Japanese Patent No. 48281 and the like has been proposed. Regarding the signal format and the decoding method of reproduced data, for example, Japanese Patent Laid-Open No. 54-752
The ones described in Japanese Patent Laid-open No. 04 or Japanese Patent Application Laid-Open No. 55-3287 are known. Furthermore, regarding error detection, for example, Japanese Patent Laid-Open No. 61-'71478, Japanese Patent Laid-Open No. 61-276175, or Japanese Patent Laid-Open No. 6
A method such as that described in Japanese Patent No. 1-80671 has been proposed.

D0 Problems to be Solved by the Invention Incidentally, in the digital signal recording and reproducing system as described above, a so-called time code (frame unit), which is tape position information or address information, is recorded simultaneously with data, and this time code is recorded simultaneously with data. It is common practice to use codes to set editing points during tape editing work.

However, data is delayed by a certain amount of time due to encoding processing during recording and decoding processing during playback. On the other hand, since the time code is not subjected to encoding or decoding processing, there is no delay. Therefore, during playback, data is output with a certain time delay relative to the time code. Although data is recorded frame by frame, the time delay of the data is a moderate value, making it difficult to control the system during editing and the like.

As a means to correct this, it is possible to delay the time code (see, for example, Japanese Patent Application No. 61-84812).However, in a system using a VTR,
The time code must always be locked to the reference synchronization signal, and any .

It is not possible to set a delay time.

The present invention was proposed in view of the above-mentioned conventional problems, and an object of the present invention is to provide a digital signal processing device that can easily control the system during editing, etc. do.

Means for Solving the E0 Problem In order to solve the above-mentioned problem, the digital signal processing device according to the present invention has a first input terminal to which digital data is supplied, and an error correction code for the digital data. an encoder that forms a transmission signal by dividing the signal into blocks into multiple words, a first output terminal that outputs the transmission signal, and a second input terminal that is supplied with the transmission signal;
A decoder that performs error correction decoding of the transmission signal and restores the digital data, and a second output terminal that outputs the restored digital data, the amount of data delay in the encoder and the decoder is the delay amount of the same word included in the digital data supplied to the first input terminal, the transmission signal output from the first output terminal, and the transmission signal supplied to the second input terminal. The present invention is characterized in that the sum of the delay amount of the same word included in the digital data outputted from the second output terminal is set to be an integral multiple of the block length of the blocking.

F8 Effect According to the present invention, the amount of data delay in the encoder and decoder is set to an integral multiple of the block length of the block when forming the transmission signal in the encoder, making it easy to control the system during editing, etc. becomes.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

G-1. Digital Signal Recording and Reproducing System First, the overall configuration of the digital signal recording and reproducing system will be explained with reference to FIG. This system is composed of a digital signal processing device IO and a VTR 20, and is configured to process digital data and time suites (for example, SMPTE).
It records and plays back time code (or EBU time code). The digital data and time code are recorded frame by frame.

The digital signal processing device IO includes first and second input terminals 11.12, an encoder 13, and a decoder 1.
4, and first and second output terminals 15 and 16. In addition, the VTR 20 may be, for example, a 525/525/
It is compatible with the 3ONTSC television system,
Video signal input terminal 21, video signal output terminal 22. Time code input terminal 23. and a time code output terminal 24.

The digital data D1 supplied to the input terminal 11 is error-corrected encoded and interleaved by the encoder 13, and is divided into blocks in units of multiple words (in this embodiment, 5880 words (1 frame) as described later). A pseudo video signal VPO, which becomes a transmission signal, is formed. This pseudo video signal VFII is output from output terminal 15.
The video signal is output from the VTR 20, supplied to the video signal input terminal 21 of the VTR 20, and recorded as a video signal on a magnetic tape (not shown).

Pseudo video signal VFI reproduced by the above VTR 20
is output from the video signal output terminal 22, and is output from the input terminal 12.
supplied to This pseudo video signal V□ is sent to the decoder 14
After the data portion is extracted, the data is deinterleaved and subjected to processing such as error correction decoding, and the restored digital data D is output from the output terminal 16. There is.

Here, the interleaving length of the above-mentioned interleaving during recording can be selectively switched between a plurality of types It (in this embodiment, two types 111).

The amount of data delay in the encoder 13 and decoder 14 is determined by the amount of delay of the same word included in the digital data DI supplied to the input terminal 11 and the pseudo video signal VIJ11 outputted from the output terminal 15, and the amount of delay of the same word included in the digital data DI supplied to the input terminal 11 and the pseudo video signal VIJ11 outputted from the output terminal *4Q video signal supplied ■□ and output terminal 16
The sum of the delay amount of the same word included in the digital data D0 outputted from the digital data D0 is set to be an integral multiple of the block length (one frame) of the above-mentioned blocking at the time of recording (at the time of encoding). The switching of these interleave lengths and the setting of the data delay amount will be described in detail later.

Further, the time code TCI supplied to the terminal 31 is supplied as is to the time code input terminal 23 of the VTR 20, and is recorded on a magnetic tape (not shown). Above VTR2
The time code T, played by 0. is output from the time code output terminal 24, and this is output from the terminal 32.

Although not shown in FIG. 2, the digital signal processing device 10 is provided with a delay circuit for delaying the time code by a predetermined frame during dubbing. This will be explained in detail later with reference to FIG.

G-2. Signal Format Next, the signal format will be explained. The sampling frequency corresponds to two types, 44.1 kHz and 44.056 ku2, and thereby the horizontal synchronization frequency and vertical synchronization frequency of the pseudo video signal and the data transfer rate are made different. That is, when the sampling frequency is 44.1 kHz, the horizontal synchronization frequency 1
5.75kHz, vertical synchronization frequency 60Hz, transfer rate) 3.5831 Mbit/sec, and in the case of 44.056kHz, horizontal synchronization frequency 1
The frequency is 5.734kHz, the vertical synchronization frequency is 59.94H2, and the transfer rate is 3.5795 Mbit/see.

The l data block is shown in Figure 3 (A) or Figure 3 CB.
), in the diagram consisting of 12 words, R
is the right channel sample word and L is the left channel sample word. Further, P is a parity check word for error correction, and C is an error detection word by CRCC. Also, the subscript indicates the word number, n''0.1.2..., and each word consists of 16 bits.In the odd block shown in Figure 3(A), parity check is performed. Word P.

is generated from the sample word R1. Also, parity check word P. , I is the sample word L. 4
From 1T R4m+1, parity check word P.

1 is generated from sample word R61l, 1+L4B, and 8, respectively. Furthermore, the error detection word C in the first row
1 is sample word R411+L&11411Rt
Generated from ha*x. Furthermore, the error detection words C1, 8 in the second row are parity check words P. , P&1ll
From lI+ Pa5ss, error detection word C in the third row
1 or is sample word L 611+ Rh** +
+L h*** are respectively generated.

Similarly, in the even numbered blocks shown in FIG. 3(B), the parity check word P 4a+i P411
441 Pa, y, generation and error detection word C&
+a*l+C4111S and Cis*a are generated.

Here, the digital signal processing device in this embodiment is
It has two formats with different interleave block lengths, that is, interleave lengths, and can be selectively switched. Of the two types, the conventionally used format (hereinafter referred to as the conventional format) has an interleave length of 35H (H is the horizontal period), and the newly proposed format (hereinafter referred to as the conventional format) has an interleave length of 35H (H is the horizontal period).
The new format) has an interleave length of one frame (490H).

That is, in the case of the conventional format, one interleave block consists of 35 data blocks in which the above-mentioned odd blocks and even blocks are arranged alternately, as shown in FIG. 4(A). Interleaving is shown in Figure 4 (
As shown in B), from the 1st block to the 35th block, first, the words in the first row are arranged sequentially, and then the words in the second row are arranged sequentially.
This is done by arranging the words of the row and finally the words of the third row, respectively. Each interleaved word forms a pseudo video signal as 12 words for IH. Therefore, one entire interleave block (12×35=420 words) corresponds to 35H.

In addition, in the case of the new format, the first interleave block consists of 490 data blocks as shown in FIG. 5(A), and the interleaving starts from the first block as shown in FIG. This is done by sequentially arranging the words up to the 490th block in the same way as in the conventional format. An entire interleaved block (12×490-5880 words) will correspond to one frame (490H) of the pseudo video signal.

The new format mentioned above has a very high ability to correct burst errors because the interleave block is as long as one frame. be.

In addition, in the conventional format, the interleave length is 35
Since it is short (H), the time difference between data at the input and output terminals during simultaneous monitoring during recording is small, but it is somewhat longer in the new format.

Therefore, for example, by using the conventional format for recording and reproducing audio data for audio and using the new format for recording and reproducing data for non-audio computers, etc., the requirements for both audio and non-audio applications can be met. can be fulfilled at the same time.

Note that de-interleaving is performed by a process opposite to interleaving.

The IH period of the pseudo video signal is shown in Fig. 6. The numerical values in this Fig. 6 represent the bit length, and the IH period is 6.
3.492μsec (sampling frequency 44.1
kHz), and when the sampling frequency is 44.056kHz, the lH period is 63
．． It becomes 556 psec. Each data is subjected to NRZ modulation, with "0" corresponding to the black level and "1" corresponding to the white level.

The first 8 words (128 bits) and the remaining 4 words (64 bits) of the 12 words of data between IHMs
A 1-bit control bit is inserted between the two.

Each field (odd field and even field) of the pseudo video signal begins with an equalization pulse portion preceding the vertical synchronization signal, as shown in FIGS. 7A and 7B.

In addition, the data area starts from the 177th horizontal line in odd fields as shown in FIG. 7(A), and in even fields starts from the 17.5th horizontal line as shown in FIG. 7(B). It starts from a horizontal line.

Further, the data area occupies a period of 245H in each field. That is, the data area occupies a period of 490H in one frame.

By the way, as shown in FIG. 8, the above control bits, which exist one bit each in IH, are 35H, that is, 35 bits of 4, ~b, and 4 as one block, and the first bit, ~bs, The following ratios are made for 4 bits.

b,...Emphasis ON: Data "0" OFF: Data 11" b,...Sampling frequency 44.1kHz: Data "O" 44.056kHz: Data"l'b Wealth...Format New format: Data ``θ'' Conventional format: Data ``1'' b, ...Audio/non-audio Non-audio: Data ``O'' Audio: Data ``1'' Note that the remaining 31 bits of ~bsa are not calculated in proportion. All values are set to 1".

G-1 Encoder Next, an example of a specific block circuit configuration of the encoder 13 will be described with reference to FIG. 9. A pair of input terminals 41 and 42 are supplied with left channel digital data (sample word) DlL and right channel digital data (sample word) Dl, respectively, and this is, for example, a memory IJ43 having a capacity for 4 interleave blocks. written to. The memory 43 is supplied with each address information from a write address generator 44 and a read address generator 45, and a timing signal from a timing generator 46, and controls address and timing during writing and continuous output. It is about to be done. The write address generator 44 and the read address generator 45 are supplied with a format off signal from a terminal 47. The a signal Fsv controls switching of address information to be output. Note that timing signals are also supplied to the write address generator 44 and read address generator 45 from the timing generator 46, respectively.

Then, the data is sequentially read out from the memory 43 and subjected to error correction encoding, as well as interleaving.

That is, in the example shown in FIG. 4 or FIG. 5, for the first row, first, sample word R0 is successively output, and this is selected by MPX (multiplexer) 48. Next, sample word L+ is read out. The sample word R8 is then read out and selected by the MPX 48. These three sample words R@, L+
, Ri are sequentially supplied to the CRCC generator 49,
An error detection word C0 is generated, which is transmitted to the MPX48 above.
is selected at the following timing. The processing for the first row is completed by repeating the above operations.

Regarding the second row, first, sample word R0 and sample word L are read out simultaneously, and these are supplied to parity generator 50 to generate parity check word P. Then, the parity check word P0 is selected by the MPX 48. Then, the sample words L1 and R1 are read out simultaneously, and the parity check word P is generated in the same way.
8, then the sample word R8, L
m are simultaneously read out, and a parity check word P3 is similarly generated and selected by the MPX 48. These three parity check words Pa, P+,
Pg is sequentially supplied to the CRCC generator 49 to generate an error detection word C8, which is selected by the MPX 48 at the next timing. The processing for the second row is completed by repeating the above operations.

The processing for the third line is the same as for the first line,
The explanation will be omitted. Note that the MPX4B is supplied with a timing signal from the timing generator 46.

The output from the MPX 48 is supplied to a pseudo video signal forming circuit 53 via a control bit insertion circuit 52 for inserting control bits supplied from a control bit generator 51, and is output from an output terminal 54 as a pseudo video signal VPO. It is now possible to do so. The control pit generator 51. Control bit insertion circuit 52. A timing signal is supplied from the timing generator 46 to the video signal forming circuit 53 and the wi-order video signal forming circuit 53, respectively.

The control pit generator 51 also receives the format cutoff signal Fsw supplied from the terminal 57.
The switching of control bits to be output is controlled by.

In the encoder 13 having such a configuration, the write address generator 44 . Read address generator 45.
Each operation of the control pit generator 51 and the control pit generator 51 is controlled by switching, and support for two types of formats (conventional format and new format) with different interleave lengths is attempted.

G-4. Decoder Next, an example of a specific block circuit configuration of the decoder 14 will be described with reference to FIG. 1O. The input terminal 61 has the signal being played from the VTR 20! ! A video signal VP+ is supplied to the right side of the data separator 62 and to the sync separator 63, respectively. In the data separator 62, the supplied pseudo video signal VP
A data portion (including control bits) is extracted from I and supplied to a CRCC checker 64 and a control bit extraction circuit 65, respectively. Further, the sync separator 63 extracts a sync signal portion from the supplied m4E1 video signal □, and supplies this to the timing generator 66.

The data separator 62. CRCC checker 64,
Timing signals are supplied from the timing generator 66 to the control bit extraction circuit 65 and control bit extraction circuit 65, respectively, so that the timing of each operation is controlled.

The CRCC checker 64 detects errors in 4-word units, and 3-word data and error detection flags for each unit are sequentially written to a memory 67 having a capacity of, for example, one interleave block. be included. In the example shown in FIG. 4 or 5, first,
Three sample words R, , L, , Rt and their corresponding error detection flag F'co are written in the 0th order, and three sample words Lx, Ra, Ls and their corresponding error detection flag Fcs are written. be included. In this way, data is sequentially written into the memory 67.

The control bit extraction circuit 65 extracts the control bit inserted between the data and supplies it to the switching control circuit 68. A switching control signal according to the format is output from this switching control circuit 68, and a writing address generator 69 and a continuous address generator 70 are output.
and delay circuits 77 and 79, which will be described later. The write address generator 69 and the read address generator 70 are controlled to switch output address information by the switching control signal. This allows support for two types of formats with different interleaving lengths. The memory 67 is supplied with each address information from the write address generator 69 and the read address generator 70, and a timing signal from the timing generator 66, and performs address control and tie checking during writing and reading. control is now in place. Note that timing signals are also supplied from the timing generator 66 to the write address generator 69 and the read address generator 70, respectively.

Then, data is sequentially read out from the memory 67.
Interleaving is performed and error correction decoding is also performed. That is, in the example shown in FIG. 4 or FIG. 5, first, the sample words L, Re, and the parity check word P in the first column of the first block, and the error detection flag for 3 bits for these are detected. F and are read out at the same time. The correction circuit 71 generates a correction value Re' from the sample word L and the parity check word P, and the correction circuit 72 generates a correction value Re' from the sample word R and the parity check word P. Also,
In the parity checker 73, sample words Ls, Re
Syndrome calculation is performed from and parity check word P. The MPX 74 is supplied with the 3-bit error detection flag F3, the output from the parity checker 73, and the timing signal from the timing generator 66, and a switching operation is performed based on these. That is, if no error occurs, the sample words L-, Re from the memory 67 are MP
If an error occurs, the correction value Le' from the correction circuit 72 or the correction value R0° from the correction circuit 71 is selected by the MPX74. Thereafter, processing is similarly performed in the order of data in the second column of the first block, data in the third column, data in the first column of the second block, and so on.

The left channel output and right channel output from the MPX 74 are supplied to interpolation circuits 75 and 76, respectively. This interpolation circuit '75.76 performs average value interpolation or previous value hold when an error occurs in data and cannot be corrected. Here, in the case of a new format with an interleave length of 1 frame, the above-mentioned interpolation circuit 75.76 has a high correction ability for burst errors.
It is considered unlikely that this will work when a conventional format with an interleaving length of 35H is used.

The output from the interpolation circuit 75 is sent via a delay circuit 77 to an output terminal 78 as digital data I)o of the left channel.
Further, the output from the interpolation circuit 76 is outputted from the output terminal 80 via the delay circuit 79 as the right channel digital data D. Output as evening. The delay amount of the delay circuits 77 and 79 is controlled by a switching control signal from the switching control circuit 68.

Here, the setting of the delay amount of the delay circuits 77 and 79 will be explained using a new formant with an interleave length of 1 frame (490H) as an example. In FIG. 2, during recording, a time code TCI is supplied to the terminal 31, and digital data DI is supplied to the input terminal 11. The timing of these time code TCI and digital data D1 is, for example, as shown in FIG. The relationship is as shown in A). That is, the word th digital data D exists at the beginning of the nth frame of the time code Tel, which has a unit of 1 frame, and the +1470th word exists at the beginning of the n+1 frame. For subsequent frames as well, at the beginning of each frame there will be a word obtained by adding 1470 to the word located at the beginning of the previous frame. Note that here we are focusing on data for only one channel, and 3 per IH.
Word 7 (1 frame: 3X490-1470
Of course, a parity check word and an error detection word are not included.

Next, in FIG. 2, a time code T is output from the terminal 32. As shown in FIG. 1(B), the timings of the digital data D and the digital data D outputted from the output terminal 16 are shifted by three frames compared to the time of recording described above. That is, for example, the word of the digital data D is at the beginning of the n+3 frame of the time code T'co, and the k+1470th word is at the beginning of the n+4 frame. Of course, the 1 word and 1470 word of this digital data D0 are the same words as the 2 word and 1470 word of the input digital data D1 at the time of recording described above. Without the delay circuit 77 or 79, the amount of data delay would be, for example, about 2 frames + 5 words.
3 and the data delay amount in the decoder 14 is exactly 3 frames (4410 words).As a result, by subtracting 3 from the value of the frame with the reproduced time code Tc0, you can determine at what timing the data was recorded. This makes it easy to control the system during editing, etc. For example, even when rewriting only one frame, it is easy to set the data input timing.

G-5. During dubbing Also, as shown in FIG. 11, a delay circuit 17 is provided in the digital signal processing apparatus 10 for delaying the time code during dubbing. The delay circuit 17
The amount of delay is set equal to the amount of data delay with respect to the time code (in the above example, 3 frames), and the pseudo video signal at the video signal output terminal 91 of the VTR 90 on the playback side and the time code output terminal 92 are Timing relationship with time code and recording side VTR
The timing relationship between the pseudo video signal at the video signal input terminal 101 of the IOO and the time code at the time code input terminal 102 can be kept equal.

In the case of the conventional formant with an interleaving length of 35H, the delay amounts of the delay circuits 77 and 79 are controlled so that the data delay amount in the encoder 13 and decoder 14 is exactly l frames. . In this case, it goes without saying that the delay amount of the delay circuit 17 is set to one frame.

H0 Effects of the Invention As is clear from the description of the embodiments described above, according to the digital signal processing device according to the present invention, the amount of data delay in the encoder and decoder is reduced by pronking when forming a transmission signal in the encoder. By setting the length to an integral multiple of the block length, the system can be easily controlled during editing and the like.

[Brief explanation of the drawing]

Figures 1 to 11 are diagrams for explaining one embodiment of the present invention, with Figure 1 being a time chart showing the timing of time codes and digital data, and Figure 2 showing a digital signal recording and reproducing system. A block diagram, FIG. 3 is a diagram showing the structure of a data block, FIG. 4 is a diagram showing the conventional format, FIG. 5 is a diagram showing the new format, FIG. 6 is a waveform diagram showing the IH period of the pseudo video signal, FIG. 7 is a waveform diagram showing each field of the pseudo video signal, FIG. 8 is a diagram showing one block of control bits, FIG. 9 is a block diagram showing an example of a concrete block circuit configuration of the encoder, and FIG. The figure is a block diagram showing an example of a specific block circuit configuration of the decoder, and FIG. 11 is a block diagram for explaining the operation during dubbing. 10...Digital signal processing device 11.12...Input terminal 13...Encoder 14...Decoder 15.16...Output terminal

Claims (1)

[Claims] A first input terminal to which digital data is supplied; an encoder that encodes the digital data into error correction codes and blocks each word to form a transmission signal; a first input terminal that outputs the transmission signal; a second input terminal to which the transmission signal is supplied; a decoder that performs error correction decoding of the transmission signal and restores the digital data; and a second input terminal that outputs the restored digital data. an output terminal, the amount of data delay in the encoder and the decoder is included in the digital data supplied to the first input terminal and the transmission signal output from the first output terminal. The sum of the delay amount of the same word and the delay amount of the same word included in the transmission signal supplied to the second input terminal and the digital data output from the second output terminal is the block length of the blocking. A digital signal processing device characterized in that the digital signal processing device is set to be an integer multiple of .