JPS63312755A - Code converter - Google Patents

Abstract

PURPOSE:To obtain timing information without the rise of a transmission speed by converting to a parallel pulse signal, inverting the special bit level value of a pulse signal to continue a same level value and converting and sending to a serial pulse signal. CONSTITUTION:An incoming serial pulse signal of (m) bits is converted to a parallel signal by a serial parallel conversion circuit 2. Then, based on a parity counting result to count an (m-1) number of bits in a parity counter circuit 3 excluding the i-th bit of an output signal in the circuit 2, the level value of the i-th bit is inverted in a violation circuit 4. The bit formed by a violation means is inserted into the i-th of the (m-1) number of bits free from the i-th bit and converted and sent to a serial pulse signal in a parallel serial conversion circuit 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to code conversion means for supplying codes suitable for digital transmission lines.

Summary of the Invention] The present invention is a means for generating a code suitable for a digital transmission line that requires timing information, by inverting the level value of a specific bit of a pulse signal in which the same level value continues based on a rule. This makes it possible to generate codes that meet the requirements without increasing the transmission speed.

[Conventional technology]

A code suitable for a transmission line is a transmission line signal that does not depend on human input signals, so-called BSI (Bit 5eq
-uence independence).

That is, when the input signal is a human input signal such as an image digital signal or a data digital signal,
l r(] + or allrl". However, on the general digital relay transmission side, regenerative relay is performed and timing information is required. AllrQ" or all +"1 is used as a transmission path signal. ．．
If J does it manually, timing information cannot be obtained,
Relay transmission becomes impossible.

Therefore, selecting a code suitable for the transmission path is an essential condition for a relay transmission system. Conventional codes suitable for this type of transmission path include mBnB codes and CMI codes that convert m-bit codes into n-bit (n>m) code strings.

[Problem that the invention seeks to solve]

However, when such conventional mBnB codes and CMr codes are used, there is a drawback that the transmission speed increases. For example, for mBnB codes, the speed increase is n/m times, and for CMI codes, the speed is doubled. This is not much of a problem in the case of low-speed digital transmission, but
When the speed increases, for example, in Gb/s transmission, the absolute value becomes large even with a small increase rate, which causes problems such as band limitation, and has the disadvantage that long-distance transmission becomes impossible.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks, and aims to provide a code conversion device that converts signals into a format in which timing information can be obtained without increasing the transmission speed.

[Means for solving problems]

The present invention includes a first converting means for converting an incoming m-bit serial pulse signal into a parallel pulse signal, and a first converting means for converting an incoming m-bit serial pulse signal into a parallel pulse signal, and dividing the first bit of the parallel pulse signal ((tr.

-1) counting means for counting the parity of the bits; violation means for generating a bit by inverting the level value of the first bit based on the counting result of the counting means; and the i-th bit. was removed (m-
1) a second conversion means for inserting the bit generated by the violation means into the first of the bits and converting the generated parallel pulse signal into a serial pulse signal and transmitting the serial pulse signal. .

[Effect]

After separating the human signal pulse train into m-bit parallel pulses, 1 to l−■ and i+l excluding the first pulse
- Count the parity of the mth pulse train. Using the counting results, for the i-th pulse train, for example,
An operation is performed in which a violation is applied in the case of even parity, and a violation is not applied in the case of odd parity, to form one pulse train again. The receiving side restores the arriving pulse train using the same violation rule.

〔Example〕

Hereinafter, one embodiment of the present invention will be described based on the drawings. 1st
The figure is a block configuration diagram showing the configuration of this embodiment.

This embodiment includes a serial/parallel conversion circuit 2 which is a first conversion means for converting an incoming m-bit serial pulse signal into a parallel pulse signal, and a serial/parallel conversion circuit 2 which is a first conversion means for converting an incoming m-bit serial pulse signal into a parallel pulse signal. ) parity counting circuit 3, which is a counting means for counting parity for bits; and a violation means, which is a violation means, which generates a bit by inverting the level value of the first bit based on the counting result of this counting means. circuit 4 and converting the parallel pulse signal generated by inserting the bit generated by the violation means into the first of the (m-1) bits from which the first bit has been removed, into a serial pulse signal. A parallel-to-serial conversion circuit 5 is provided as a second conversion means for transmitting data.

Here, the rule is that m=5, the parity of the first to fourth pulse trains is counted, and a violation is applied when the parity is even, but no violation is applied when the parity is odd. Now, the pulse train from the input terminal 1 is separated into 5-bit parallel pulse trains by the serial/parallel conversion circuit 2. Subsequently, the parity counting circuit 3 counts the parities of the first to fourth pulse trains, and the violation circuit 4 applies a violation to the fifth pulse train. Thereafter, it is converted into a pulse train by the parallel-to-serial conversion circuit 5, and a 58 IP code is sent out from the output terminal 6. On the receiving side, this inverse transformation is performed to restore the original pulse train.

FIG. 2 shows an example of code conversion. (a) is a human input signal, and (b) is a 58IP code.

〔Effect of the invention〕

As explained above, the present invention has the effect of providing a code with so-called BSI that is suitable for a transmission path code without increasing the transmission speed.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a waveform diagram showing an example of code conversion. ■...Input terminal, 2...Series-to-parallel conversion circuit, 3...
Parity counting circuit, 4...Violation circuit, 5
...Parallel-serial conversion circuit, 6...Output terminal. Patent applicant: NEC Corporation,

Claims (1)

[Claims] (1) A first converting means for converting an incoming m-bit serial pulse signal into a parallel pulse signal, and excluding the i-th bit of this parallel pulse signal (m-1
) counting means for counting the parity of the bits; violation means for generating a bit by inverting the level value of the i-th bit based on the counting result of the counting means; a second converting means for inserting the bit generated by the violation means into the i-th of the (m-1) bits thus generated and converting the generated parallel pulse signal into a serial pulse signal and transmitting the serial pulse signal. A code conversion device characterized by: