JPS5885657A - Data transmitting system - Google Patents

Abstract

PURPOSE:To transmit intermittent and continuous data by one cable, by obtaining a read timing from the head bit added by the transmitting side, of a serial data transmitted through one transmission cable from the transmitting side. CONSTITUTION:That which had added information 1 to a parallel data input 10 is inputted to a prallel/serial converting circuit 11, and ''1'' and ''0'' of an obtained serial data are made wide and narrow in width, respectively, and the pulse width is modulated. Subsequently, an obtained data is transmitted through one transmission cable from an output terminal 20. In the receiving side, a serial data (i) inputted from a terminal 35 is inputted to a terminal D of a shift register 22, and also is inputted to a clock terminal T through a delaying circuit 21. As a result, from output terminals Q1-Q8, a parallel data is outputted in reverse order. Also, by the head bit information 1 added by the transmitting side, which has been outputted to a terminal Q9, a one shot circuit 23 is started. An output (k) of this circuit 23 and the outputs Q1-Q8 of the register 22 are inputted to AND circuits 25-32, and a parallel data 33 is obtained.

Description

[Detailed Description of the Invention] The present invention relates to a data transmission method, and particularly to a data transmission method suitable for intermittent and continuous data transmission using only one cable and requiring no clock extraction circuit. .

In each controller of data communication equipment, electronic communication equipment, input/output processing equipment, mobile radio equipment, etc., the parallel information of the word configuration data is converted into serial information and the necessary falsification is performed.
Data transmission and processing are performed by converting the demodulated serial information into parallel information on the controlled device side.

Figure 1 shows the system of the data transmission system, and 1 is the control 9.
．． 2 is a parallel/serial conversion circuit that converts parallel data from the controller 1 into serial data, S is a serial data transmission cable, 4 is a serial/parallel conversion circuit that converts serial data into parallel data, and 5 is a controlled device. It is. Assuming that the same configuration is used as a control unit for an automatic military telephone, the controller 1 corresponds to a handset, the transmission cable 3 corresponds to a curl cord, and the controlled device 5 corresponds to the telephone main body.

In Figure 1, the controller 1, which is the data transmitting side,
Then, '11, which is a data head identification signal, is added to the beginning of the parallel binary digital information having a certain number of pits (CN), and f5 (N + 1) pieces of data are converted into (N+1) pieces of data in the parallel/serial conversion circuit 2. Convert to pulse width modulated serial data. This serial data is transmitted via one transmission cable 3, and on the receiving side, a serial/parallel conversion circuit 4 converts the N pieces of serial data into parallel data.

The data is input to the controlled device 5 as the original parallel data, and the controlled device 5 extracts and reproduces the data head identification signal, then decomposes the received data contents and performs the necessary operations.

Further, FIG. 2 shows another example, in which the system shown in FIG. In the same figure, those with the same - sign as in the fK1 diagram have the same 411 functions, but 6 is the control a+11I.
Nine serial/parallel conversion circuits are provided in the IK, 7 is an input/output circuit on the controller side, 8 is an input/output circuit on the controlled device side, and 9 is a parallel/serial conversion circuit. In addition, the controller 1 and the controlled device 5 transmit a precise control signal to the input/output circuit wI to select the direction of whether each device is on the receiving side or the transmitting side.
7 and 8 are entered.

In this circuit, one transmission cable 3 is used to transmit data from the controller 1 and the controlled WM 500,000, and hp1 is transmitted in both directions to the receiving side. Controller 1. The information may be decoded by the controlled device 5, or may be transmitted alternately. For direction control in this case, the order in which the first signals arrive is determined in advance, and the input/output circuits 7 and 8t are opened accordingly, allowing smooth signal transmission and reception.

1 above. As shown in the second example, in addition to the method of converting parallel data to serial data and transmitting the data using a single transmission cable, there is also a method of transmitting the data in parallel using approximately the same number of cables as the number of data. However, this method has the disadvantage of requiring a large number of cables. t+
.

Although the method shown in FIGS. 1 and 2 described above can overcome such drawbacks, the clock signal is extracted and reproduced on the receiving side in order to demodulate the data.

It was unsuitable for sending data intermittently, and to avoid this, a dedicated cable was required to send the clock signal separately. Namely.

At least two transmission cables were required for continuous data transmission.

The purpose of the present invention is to eliminate the need for a clock signal extraction circuit on the receiving side, to be able to reliably extract data even from intermittent data, and to use only one transmission cable to connect devices. The purpose is to provide a data transmission method that is easy to use.

In the present invention, on the data transmitting side, parallel data consisting of counting bits is converted into serial data with one bit of information "1m" added to the beginning, and the serial data is pulse width modulated and transmitted. The receiving side, which receives the pulse-modulated serial data via a single transmission cable, detects the first pulse waveform change point in one bit period and uses the detected data to convert the received serial data. It is reproduced into a parallel NRZ code, and the next leading bit and g are added to obtain the parallel data reading timing, so that even if the received data is IIfr continuous data, it can be reliably extracted and reproduced. .

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIGS. 3 to 6. FIG. 3 shows a circuit section 551 of a pulse width modulation transmission code converter, which corresponds to the first parallel/serial conversion circuit section. It was. Similarly, FIG. 5 shows the circuit configuration of a pulse width modulation receiving code converter.

#! This corresponds to the serial/parallel conversion circuit section shown in FIG.

In Fig. 3, IQ is parallel data output from the controller, 11 is a parallel/serial conversion circuit, and has parallel data input terminals -, D, and terminal 1 for inputting head information @1m. ing.

Also, 12Fi clock signal input terminal, 15ij
Delay circuit, 14Fi one-piece circuit-'5+ 16.
19 is an f-marked circuit, 17 is an OR circuit, and 18 is a one-shot circuit, which are connected as shown. And, the output terminal 20 of the wood-picking circuit 19 is connected to one transmission cable.

Next, the circuit operation of the same configuration is #! This will be explained with reference to the time chart in FIG. The transmission code conversion circuit that performs this pulse width modulation receives 1 m of information in addition to the parallel data input 10.
is input to the parallel/serial conversion circuit 11 by the clock signal α, where the serial N'
It is output as RZ code "101100011Jb.

Then, j! is set so that the high level of clock signal 6 comes within the bit period of the NRZ code. J at Enharo 15! The extended clock signal C is input to the 14NI) circuit 15,
Obtain a wide "1" axis conversion output card for the NRZ code. −
10, the narrow negative pulse d obtained by the one-shot circuit 14 activated at the rising edge of the delayed a-sock signal C, and the NRZ
The code 〇-information is input to the 14ND circuit 16, °
Obtain the narrow width A/ corresponding to Om, and the X column fk. The pulse train d and f are inputted to the F-1OR circuit w117 to obtain a pulse train l which is synthesized by one. Here, one-shot circuit 18 is 1 synthesis Haru's sorrow! This is to create a gate pulse to be input to the AND circuit 19 together with the pulse train 1 in order to remove the unnecessary pulses marked with an "X" in the figure, thereby making the one-shot pulse width match the effective serial data length. In this way, the transmitted code is obtained from the output terminal 2o.

Note that during the same-plane transmission, the delay circuit wt15 is not essential, and the one-circuit delay circuit '*' can be omitted depending on the receiving method. Furthermore, a similar pulse train can be obtained from the output terminal 20 by replacing K with a negative circuit. moreover,
The one-shot circuit 18 and the attendant circuit 19 are also made unnecessary by the receiving signal method.

Serial transmission code ji obtained as the circuit output of Fig. 3
The signal is transmitted to the receiving side via one transmission cable tube and is pulse width modulated, and the reception code conversion circuit is as shown in Figure tI45. Also.

The input/output waveform diagram of each part of the circuit is as shown in FIG. The reception code conversion circuit shown in FIG.

A data delay circuit 21 that receives serial data from the terminal 35. Shift register 22. A one-shot circuit 25 which inputs the output data from the output terminals Q and -Q of the shift register 22. The output signal k of the one-shot circuit 25 is input.

A one-shot circuit 24 for resetting the shift register 22 and each output Q of the shift register 22, -
It consists of circuits 25 to 52 which calculate the AND of the output signal obtained through the one-shot circuit 25 and the output signal obtained through the one-shot circuit 25. Note that terminals l) 1 to D are parallel data 3St.
- It is connected to a controlled IBK as shown in FIGS. 1 and 2.

tq, that is, the circuit configuration of the ms diagram is 7v bit information @K"
The serial data of A'+1 having a leading billeter of 1" is received using a pulse width f true wave with a wide width of 11" and a narrow width of 0", and c is small, e = narrow pulse width is larger than j! m*
The received pulse delayed by a delay circuit having a delay circuit is used as an input.

An N + 1 bit shift register that uses the received pulse as a data input, and a second stage of the W/Set circuit are manually inputted to the N + 1st output of the register, and the output pulse of the vk stage is used to The configuration is such that the register is reset, and the NII-th output pulse from the beginning of the register and the output pulse of the previous stage of the one-shot circuit are respectively input to N AND circuits to generate parallel data of N pits. That's how you get it.

Next, the operation will be explained according to FIGS. 95 and 6.

In the tIILS diagram, first, serial data "101100011" i inputted from the terminal 35 is inputted to the data input terminal DJ/C of the shift register 22.

The input data that has passed through the delay circuit 21 having a delay amount larger than the narrow pulse width is input to the clock input terminal T, and at the rising edge of the delayed data, the data becomes false. Parallel data is output from the output terminals Q, -Qa of the shift register 22 in reverse order. In addition, the one-shot circuit 23 is activated by the additional a priori bit information %'1' in the transmission pulse outputted to the output terminal Q, and a wide one-shot circuit 23 is generated, and the rising edge of this pulse The narrow width pulse t1 shown in FIG. 6 from FIG.
The sum is determined to be smaller than the bit period. AND circuit 25 ~ as a gate pulse for one-shot pulse
32, are jointly input with the outputs Q1 to Q8 of the shift register 22, and are outputted to the control signal terminal 34 and used as a control signal to the subsequent circuit. Then, Q1 to Q are reset to @01 in preparation for the next input data processing.

Therefore, it is clear that even if input data arrives continuously rather than intermittently, serial data can be converted continuously into parallel data without any problem. It can be used regardless of the speed of continuous data as long as the sum of the pulse widths of the circuits 25 and 24 does not exceed the bit period t. *For intermittent data transmission and reception, if the intermittent data interval is long enough.

The effective speed range of data is larger than that of continuous data.
In either case, there is no problem with slow data speed.

Next, as another application example, as shown in Figure 2, even if two-way data is transmitted and received using a single transmission cable, by adopting the data transmission method described above, even if intermittent data is received, it will not occur. can be achieved. This can be accomplished by sending a control signal indicating the direction of the data as data, or alternatively by using a reciprocal transmission method.

The circuit 24 in the ti, ms diagram generates negative pulses, but in the case of negative pulse generation, the reset terminal R of the shift register 22 operates with a positive input, or the negative circuit generates negative pulses. A similar operation can be achieved by inserting the same.

As is clear from the above-mentioned examples, according to the present invention, 1
It has the advantage that intermittent and continuous data transmission is possible with a single cable, no clock signal extraction circuit is required, and the transmission speed can be set arbitrarily.

[Brief explanation of drawings]

Figures 1 and 2 are system diagrams of a data transmission system to which the present invention applies, and Figures 3 and 5 are data conversion circuit diagrams and data transmission side diagrams for explaining an embodiment of the present invention. Receiving side data conversion circuit diagram, Figure 4 and #I6
The figure is an evening chart for explaining the operations of FIGS. 3 and 5. 11...Parallel/serial conversion circuit 15.21...
・Delay circuit 14, 18.25.24... Wanshi bottom circuit 15,
11S, 19.25-32...AND circuit 17
... OR circuit 22 ... Shift V dista sugar 1 figure 2 figure 31 yen] sugar 4 figure ( figure 5 figure 6 Dl.

Claims (1)

[Claims] On the data transmitting side, the N-bit parallel data is converted into 9N+1 serial data by adding a leading bit of 11m to the parallel data, where 11' of the serial data is wide and '''Om is narrow. The pulse width is modulated as 11, and the data is transmitted via one transmission cable, and in the data reception 11, it is delayed by a delay circuit that has a delay amount smaller than the wide pulse width and larger than the narrow pulse width. The received pulse t-N + 1 bit is used as the clock input of the shift register, and the serially inputted received pulse is used as the data input, and the N + 1 bit of the register is connected to the front stage of the two-stage one-shot circuit. inputting the output of the register, resetting the shift register by the output pulse of the subsequent stage, and performing a logical product between the Nth output pulse from the beginning of the register and the output pulse of the previous stage of the one-select circuit; A data transmission method characterized by being able to obtain N-bit parallel data.