JPS63310133A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a parasitic effect and to prevent a lowering in an integration density by a method wherein a groove is filled with a conductive filler coming into contact with a semiconductor substrate via an opening which has been formed at the bottom of the groove of an insulating film. CONSTITUTION:A device region is partitioned by a groove which has been dug from the surface of an N-type epitaxial layer 4 of a semiconductor substrate formed by a P-type region 2, an N<+> type buried layer 3 and the N-type epitaxial layer 4 on a P-type semiconductor substrate sheet 1 composed of silicon toward the inside and which has been covered with insulating films 6-1, 6-2 composed of silicon oxide. The groove is filled with a conductive filler 10 which comes into contact with the P-type semiconductor substrate sheet 1 at the bottom of the groove. By this setup, it is not required to form a space for a substrate electrode region separately; an integration density of a semiconductor integrated circuit can be enhanced; furthermore, it is made possible to impress a substrate potential on all parts around individual devices; accordingly, a parasitic effect among the individual devices can be eliminated completely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a bond isolation structure.

[Conventional technology] Are recent integrated circuits more like Otani's version of 1111? To increase speed, groove separation techniques are being used.

The structure of groove separation in bipolar integrated circuits is shown as the fifth factor.
. This involves forming separation grooves each covered with an insulating film 6.5 on the side and bottom surfaces of the semiconductor substrate on which the N7-type Evitaki 7-yal NI4 is formed, and filling the inside with a filler 10 made of polycrystalline 7-lion. do.

Thereafter, the surface of the polycrystalline silicon is covered with an insulating film 7.

A predetermined impurity is selectively diffused into the device region partitioned by the °C groove to form an opening for an electrode, thereby forming a device.

Incidentally, in an integrated circuit, a minimum potential or a specific potential is applied to the substrate (the P-type semicircular base plate 1 in FIG. 3) in order to prevent parasitic effects and stabilize the characteristics of each element. Sometimes, in integrated circuits where the degree of integration is low and leakage current flows to the substrate due to the element structure, the substrate potential tends to float, which tends to cause negative effects. That is, this may lead to malfunction of the circuit or instability of characteristics.

In order to prevent this, it is necessary to raise the substrate potential in 1. In order to meet the ieF capacitance value, the substrate 11 and others must be provided at various locations and a substrate potential must be applied at a predetermined potential.

[Problem that the invention seeks to solve]

The above-described conventional semiconductor integrated circuit using four isolations has an insulating film on the bottom of the isolation groove, and cannot be electrically connected to the substrate. In other words, in the conventional semi-integrated circuit using groove separation, it is necessary to provide the substrate electrode portion in a space to prevent parasitic effects, which has the disadvantage that the degree of integration is reduced accordingly.

In particular, if the above-mentioned substrate electrodes are inserted every few rows in a large-scale array such as a memory, there is a drawback that the integration efficiency is extremely reduced and the speed characteristics are deteriorated. [Means for Solving the Problems] The semiconductor integrated circuit of the present invention is a semiconductor device in which an element region is divided by a trench dug inward from one main surface of a semiconductor substrate and whose surface is covered with an insulating film. In the integrated circuit, the trench is filled with a conductive filler that contacts the semiconductor substrate through an opening provided at the bottom of the trench in the insulating film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a perspective sectional view of a semiconductor chip showing the main part of the first example of the present invention.

This example is a P-type semiconductor base plate IKP made of 7 silicon.
A semiconductor substrate formed with a mold region 2, an N type buried layer 3, and an N type buried layer 4 is dug inward from the surface of the Nu type layer 4, and an insulating layer made of silicon oxide is formed on the side surface. A conductive filler 10 (doped with a P-type impurity) is formed in a groove covered with a film 6-1. The grooves are filled with polycrystalline/recon.

Next, the manufacturing method of this example will be explained.

FIGS. 2A to 2D are perspective views of semi-integrated chips arranged in order of process a for explaining the manufacturing method of the first embodiment.

First, as shown in Fig. 2 (t8), a P-type region 2°N+ type lump is formed on a P-type semiconductor base plate 1 made of silicone with a crystal axis (111>, a diameter of 4 inches, a resistivity of 10 to 20Ω, and a resistivity of 10 to 20Ω). Layer 3 is formed, and on top of that is N5 with a resistivity of 5Ω and scratches.
A layer 4 is grown to a thickness of 1 μm. The thus prepared semiconductor substrate is selectively etched from the surface of the N-type epitaxial layer 4 to the P-type semiconductor substrate layer 1.
A groove of .mu.m is formed to define an element region. Next, the bottom and side surfaces of the grooves and the surface of the element region were heated at 1000°C for 10 minutes.
The insulating film made of silicon oxide is thermally oxidized for 5.6 minutes.
form 7. Next, cut the groove covered with this insulating film to a height of 1#.
The surface is made substantially flat by filling it with polycrystalline silicon 11 doped with a certain amount of boron. Note that a resist or resin may be used instead of polycrystalline silicon.

Thereafter, a resist film 2 is applied, and a band-sized pattern with a width of 1 μm is selectively formed slightly inside the buried polycrystalline/recon 11. Then, a groove 3 reaching the P-type semiconductor base plate 1 is formed by dry etching. And Figure 2 (
As shown in C), the insulating film 5 remaining at the bottom of the trench is removed by performing a Couette etching process for about 1 minute.

Next, as shown in FIG. 2(d), the resist film 12 is removed, and the polycrystalline silicon 11 remaining on the side walls of the groove 13 is removed. Here, the surface and side surfaces of the element region are all covered with an insulating film, and the groove bottom portion of the isolation region is a trap for the surface of the Pa semi-containing base plate 1 to come out.

Thereafter, as shown in FIG. 1, the above-mentioned grooves are buried up to the surface of the semiconducting body using polycrystalline silicon doped with highly concentrated boron. Then, the surface is oxidized at 1000°C for 10 minutes to form an insulating film 7 made of silicon oxide with a thickness of 0.5 μm.
form and make the surface almost flat. 1llll! on the conductive filling material 10 made of high concentration polycrystalline silicon, in which the above-mentioned groove Ka is provided at a predetermined location. ! A suitable opening is provided in the membrane 7 to form an electrode.

As is clear from the above description, the substrate potential is applied to the substrate directly below the isolation grooves through polycrystalline silicon in which highly moldy boron is diffused.

Therefore, all devices are given a substrate potential on the same day in the device area, causing malfunctions due to the electrically floating state of the substrate, property deterioration such as increased capacitance between the substrate and collector, and parasitic effects between adjacent devices. does not occur at all.

FIG. 3 is a perspective sectional view of a semiconductor device showing the main portion of the second embodiment of the present invention.

In this embodiment, an opening 14 having a width of 1 μm and a length of 5 μm is selectively sunk in the insulating film 5 in the paper trap of the groove.
This is different from the first embodiment in that the opening was provided at the entire bottom surface of the groove. In the first embodiment, if the portion under the insulating film on the side surface of the trench is thin, there is a risk that the insulation isolation will be incomplete. In the second embodiment, there is almost no such fear. This is because the width of the opening of the sword is smaller than the width of the groove.

FIG. 4 shows #! of the second embodiment. FIG. 2 is a perspective cross-sectional view of a semiconductor chip in an intermediate step for explaining the sword making method.

As shown in FIG. 2 (13), the manufacturing method for the casing is the same as that of the first embodiment.

Next, as shown in FIG. 4, a resist film 15 is applied,
A pattern of 11141 μm and 5 μm in length is selectively formed, and an opening 16 reaching the P-type semiconductor base plate 1 is formed with a depth of 4 μm by dosing and chiming. The next step is step 1.
In addition, the conductive filler is preferably polycrystalline 7-licon, but may also be a high melting point metal such as KMo or W. In that case, the insulating film on the surface The CVD method, Suba, or Ri method may be used for the formation.

〔Effect of the invention〕

As explained above, according to the present invention, the conductive filler filling the separation groove is brought into contact with the semiconductor substrate portion, and electrodes can be formed on the conductive filler as appropriate, thereby saving space in the substrate electrode area. another! There is no membership fee for CD, which has the effect of increasing the degree of integration of P-type integrated circuits.Since it is possible to apply a substrate potential to the entire surrounding area of each element, parasitic effects between each element can be reduced. Moreover, the % concentration of the element is stable, and there is an effect that the semiconductor integrated circuit can operate stably and improve its reliability.

[Brief explanation of the drawing]

FIG. 1 is a square view Bfr side view of a semiconductor chip showing the main feature of the first embodiment of the present invention, and FIG. Figure 3 is a perspective front view of semiconductor chips illustrating the main arrow parts of the second embodiment of the present invention, and Figure 4 is a perspective view of the semiconductor chips arranged in order of FIG. 5 is a perspective sectional view of a semi-integrated chip in an intermediate process for explaining the manufacturing method, and FIG. 5 is a sectional view of a semiconductor chip showing the production part of a conventional example. Body base plate, 2...P type region, 3...N+ type buried layer, 4...N
Type Ebitaki 7-year layer, 5.6.7...IP! Membrane, 8-1.8-2 Old... P-type diffusion region, 9...
・・N+ type diffusion area, 10°---filling material, 11
...Polycrystalline/Recon, 12...Resist! , 13... ditch, 14... river/opening, 15...
Old...resist film. Figure 2 Compensation Figure 2 Figure 4

Claims (1)

[Claims] In a semiconductor integrated circuit in which an element region is defined by a trench dug inward from one main surface of a semiconductor substrate and whose surface is covered with an insulating film, the semiconductor integrated circuit is configured such that an element region is defined by a trench dug inward from one main surface of a semiconductor substrate and whose surface is covered with an insulating film. A semiconductor integrated circuit characterized in that the groove is filled with a conductive filler that contacts the semiconductor substrate.