JPS6330981A - Pixel operation processor in graphic display device - Google Patents

Abstract

PURPOSE:To perform a pixel operation without applying load on a picture processor, by providing a logic operation means, and a selection means. CONSTITUTION:The logic operation means (logic operation circuit 100) performs a logic operation based on a source data SD outputted from a straight line generating means (DDA37), and a destination data DD read out from a picture memory, setting them as inputs. The selection means (selector 2) inputs an arithmetic data OD outputted from the logic operation means 100, and the destination data DD read out from the picture memory 39, and also, outputs either data selectively corresponding to a control signal CS outputted from the DDA37, and supplies it to the picture memory 39. In such way, it is possible to write again the picture data in which the source data SD is written on the destination data DD, on the picture memory 39.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a pixel operation processing device in a graphic display device, and more specifically, to a pixel operation processing device for a graphic display device. By performing logical operations based on and new source data,
The present invention relates to a pixel operation processing device for obtaining image data by combining both data and writing it into an image memory again.

<Prior Art> Conventionally, in graphic display devices, so-called pixel operation processing is used to superimpose newly supplied source data on destination data that has already been written to the image memory and write the superimposed data to the image memory again. Based on the contents of the image memory that have been rewritten after the operation is performed, the image memory is provided with a function that can be visually displayed on a CRT display device.

In order to perform the above pixel operation processing operation, conventionally, the image processing processor reads destination data already stored in the image memory and stores it in the internal memory of the image processing processor, and then the destination data that has already been stored in the image memory is read out and stored in the internal memory of the image processing processor. Necessary logic operations are performed between the image data and the source data to be written into the image memory, and the image data resulting from the calculation is written into the image memory again. and,
The rewritten image data is visually displayed on a CRT display device.

Therefore, for example, for the destination data (DD) shown in FIG. 2, the source data (DD) shown in FIG.
When overwriting SD), it is sufficient to use OR as the logical operation, and both data! Ii It is possible to obtain image data in a purely superimposed state, and when removing the source data (SD) shown in FIG. 3 from the destination data (DD> shown in FIG. 3), logical operations can be performed. It is sufficient to adopt exclusive OR as the source data (S
It is possible to obtain image data in which a portion corresponding to the graphic area of D) has been removed.

<Problems to be Solved by the Invention> In the pixel operation processing device having the above configuration, the destination data read out from the image memory by the image processing processor is stored in the internal memory of the -H image processing processor, and each pixel is Pixel operation processing is performed through a series of operations in which a logical operation is performed every time the logical operation is completed, the destination data stored in the image memory is erased, and the above operation result is written back to the image memory. It is necessary that
There is a problem that the internal memory capacity of the image processing processor required to perform pixel operations must be increased, and there is also a problem that the processing capacity of the image processing as a whole is reduced.

To explain in more detail, each pixel operation requires the operation of reading destination data from the image memory, the logical operation result sent to the image processing processor υ, and the operation of writing the logical operation result to the image memory. Moreover, the memory space equivalent to one screen is approximately IMb.
Since it will be 1 Mb in order to store one screen worth of image data in the internal memory of the image processing processor.
It is necessary to provide a large-capacity internal memory called .IT.

In addition, since logical operations must be performed on approximately IMbits worth of image data, the load on the image processing processor increases, and while the above logical operations are being performed, it becomes impossible to perform the above processing. turn into. Therefore, the processing capacity of the entire image processing is reduced.

<Object of the invention> This invention was made in view of the above problems,
It is an object of the present invention to provide a pixel operation processing device that can perform pixel operations without placing a burden on an image processing processor.

Means for Solving the Problems> In order to achieve the above object, a pixel operation processing device in a graphic display device of the present invention includes a logical operation means and a selection means.

The logic operation means inputs the source data output from the straight line generation means and the destination data read from the image memory, and performs a logic operation based on both data. Pi
! It takes as input the calculation data output from the calculation means and the destination data read from the image memory, and selectively outputs any of the above data in correspondence with the control signal output from the straight line generation means. , which is supplied to the image memory.

However, it is preferable that the logic operation means performs a logic operation corresponding to the logic operation control signal outputted from the straight line generation means.

Further, it is preferable that the selection means outputs the operation data in correspondence with the part subjected to the logical operation with the source data, and outputs the destination data itself in correspondence with the other parts. .

<Operation> If the pixel operation processing with the above configuration is installed, a straight line is generated by the straight line generation means based on the graphic data transmitted from the image processing processor, the generated straight line is written to the image memory, and the contents of the image memory are In a graphic display device that displays an image according to With the destination data read from the memory as input, the logical operation means performs a logical operation based on both data, and selects the operation data output from the logical operation means and the destination data read from the image memory. is input, the selection means selectively outputs any of the above data in correspondence with the control signal output from the straight line generation means, and the source data is added to the destination data by supplying it to the image memory. The written image data can be written into the image memory again.

In the case where the logic operation means performs a logic operation corresponding to the logic operation control signal output from the linear generation means, the source data can be transferred from the linear generation means without requiring a special logic operation control device. and a logic operation control signal can be supplied, and necessary logic operations can be performed based on the source data.

Further, when the selection means outputs the calculated data in correspondence with a portion subjected to a logical operation with the source data, and outputs the destination data itself in correspondence with other portions, It is possible to obtain image data in which only the portion of the destination data that is actually subjected to the logical operation is replaced with the operation data.

<Example> Hereinafter, embodiments will be described in detail with reference to the accompanying drawings showing examples.

FIG. 4 is a block diagram showing an outline of the graphic display device, in which a graphic data management unit manages a segment buffer (not shown) from a host computer (31) through a transmission line and a host interface (32). Data is transmitted to (33). This graphic data management section (33) arranges the transmitted data in a state that can be displayed as a graphic, assigns an identification number and priority to each graphic data, and stores it in a segment buffer. And the above segment buff? The data read from the is led to the data analysis section (34) for analysis, vector calculation processing is performed based on the start point coordinates and the end point coordinates, and the processing results are sent to the coordinate transformation/clipping section (34).
5) and multiplies it with a matrix corresponding to enlargement, reduction, rotation, translation, etc., and if necessary, clips the portion that protrudes from the frame. After that, the DDA surface control/filling unit (36) generates data that is the source of line segment generation, and if filling is required, it becomes the source of many horizontal line segments corresponding to the unfilled areas. By generating data and supplying the generated data to a straight line generator (hereinafter abbreviated as DDA) (37), intermediate coordinates in the vector connecting the starting point coordinates and the ending point coordinates are calculated and the line segment is actually created. Then, each dot corresponding to the actually generated line segment data is supplied to the pixel operation processing section (38),
The image data output from the pixel operation processing section (38) is stored in the image memory (39), and the data stored in the image memory (39) is read out by the video control section (40) to perform D/A conversion. The graphics based on the data transmitted from the host computer (31) can be visualized by converting it into an analog signal by converting it into an analog signal, and converting it into a video signal based on the color conversion table, and then supplying it to the monitor display (41). so that it can be displayed.

FIG. 1 is a block diagram showing in detail the structure of the pixel operation processing section, which has a logic operation circuit (1) and a selector (2) as its main parts.

To explain in more detail, the logic operation circuit (1) is as follows:
It is possible to select the logical operation to be performed based on the logical operation designation signal supplied from the outside, and D D
Source data (SD) output from A (37) and destination data (DD) read from the image memories (three) are supplied as data to be subjected to logical operations. And the above D D A (37
) is converted into a logic operation designation signal (a) by a decoder (3) and supplied to the logic operation circuit (1).

Further, the selector (2) is the OD A (37)
The brightness data (ID) output from the logic circuit (1) is supplied as a control signal, and the calculation result data (OD) from the logic operation circuit (1) and the destination read from the image memory (three) are supplied as control signals. tion data (DD) is supplied as selected data.

Then, when the luminance data (ID) is valid, the calculation result data (OD) is output, and the luminance data (I
D) is not valid, the selector (2) is set to output destination data (DD).
) is controlled. Further, the output data (WD) from the selector (2) selected as described above is stored in the image memory (39
).

Note that the write mode signal (b) is sent to the image memory (39).
The write timing circuit (4) that supplies the above-mentioned DD△
A start signal (C) output from (37) is supplied. When the write mode signal (b) from the write timing circuit (4) is supplied to the image memory (39), the image memory (39) is supplied to the image memory (39) during the first half of the write cycle.
Destination data (DD) is output from 9).

Pixel operation processing device (38) with the above configuration
The operation is as follows.

First, a logical operation control signal (C3) is supplied from DDΔ (37) to a decoder (3), and the decoder (3) decodes the logical operation control signal to specify a logical operation such as OR or AND. A logic operation designation signal (a>) is generated and supplied to the logic operation circuit (1), so that a desired logic operation can be performed.

Next, from D D A (37), start signal (c)
Write the source data (SD) to the timing circuit (4)
is supplied to the logical operation circuit (1), and brightness data (ID) is supplied to the selector (2).

In this state, the write mode signal (b) from the write timing circuit (4) is supplied to the image memory (39), so the image memory (39) enters the write cycle. Since the eyestnation data (DD) is output in the first half of the cycle, the logic operation circuit (1
) takes the source data (SD) and destination data (DD) as input, performs the logical operation selected by the logical operation designation signal (a), and sends the operation result data (OD) to the selector ( 21.

The destination data (DD) is also supplied to the selector (2), and if the brightness data (ID) is valid, the fish performance result data (OD) is selected, and the brightness data (ID) is If the destination data (DD) is not valid, the destination data (DD) is selected and the selected data is supplied to the image memory (39) as write data (WD>). The stored data (WD>) can be written to the image memory (39) again.

To explain more specifically, as shown in FIG. 2, source data (
SD), the logic operation control signal (C8) output from the DDA (37) may be a signal corresponding to the logical sum, and the logic operation circuit (1) uses the above destination data. (DD) and source data (SD) can be logically ORed.

Since the luminance data (ID) is valid only in the graphic area M, (e) of the source data (SD), that is, the area where a graphic exists, the graphic area 1IIt(
supplying the operation result data (OD) output from the logic operation circuit (1) to the image memory (39) in correspondence with e);
Destination data (
DD) to the image memory (39), and finally, graphic data in which the source data (SD) and the destination data (DD) are superimposed can be written into the image memory (39). .

Furthermore, as shown in FIG. 3, when erasing the source data (SD) from the destination data (DD), the logic operation control signal (C3) output from the DDA (37) may be a signal corresponding to the exclusive OR, and in the logic operation circuit (1), the destination data (DD) and the source data <S
O) exclusive OR operation can be performed.

Since the luminance data (ID) is valid only in the graphic area (g) of the source data (SD), that is, the area where a graphic exists, a logical operation is performed in correspondence with the graphic area (q'). The operation result data (OD) output from the circuit (1) is supplied to the image memory (39), and destination data (DD) is stored in correspondence with the remaining area.
is supplied to the image memory (39), and finally, graphic data obtained by erasing the source data (SD) from the destination data (DD) can be written into the image memories (3). .

In addition, if the graphic data temporarily erased as described above is used as destination data (DD>) and the exclusive OR operation is performed again with the source data (SD), -time erasure can be resolved. Destination data (DD) in its original state is obtained.

As is clear from the above description, in the above embodiment, the OD
Destination data (DD) and source data (SD) are processed by the pixel operation processing unit (38) provided between
It is possible to perform a logical operation with the image data and rewrite the image data into the image memory (39). That is, since the pixel operation processing section (38) is configured in terms of hardware, it is possible to perform pixel operations at high speed without constraining the image Brossener at all.

<Effects of the Invention> As described above, the present invention allows pixel operations to be performed without placing a burden on the image processor, and moreover, performs logical operations and writes during the write cycle to a normal image memory. This has the unique effect of being able to perform high-speed drawing processing, and further improving the processing efficiency of the entire graphic display device by reducing the burden on the image processing processor. play.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the pixel operation processing device of the present invention, FIGS. 2 and 3 are schematic diagrams showing specific examples of pixel operations, and FIG. 4 shows the strategy of the graphic display device. Block Diagram. (1)...Logic operation circuit, (2)...Selector, (
3)...Decoder, (37)...DDA, (38)
...Pixel operation processing unit, (39)...
Image memory, (DD>...destination data, (SD)
... Source data, (OD) ... Calculation result data, (ID) ... Luminance data, (C8) ... Logical operation designation signal, (a) ... Logical operation designation signal Patent applicant Daikin Kogyo Co., Ltd. (Idiot 3':6) Figure 2

Claims (1)

[Claims] 1. Diagram transmitted from the image processing processor straight line generation means based on the shape data. Generate a line and display the generated straight line in the image based on the contents of the image memory. A graphic display that displays images In the ray device, the output from the straight line generating means is input source data, and image notes destination read from Logic based on both data with data as input Logical calculation means for performing calculations and logical calculations calculation data output from the means, and Destiny read from image memory - Input the motion data and use a straight line. Compatible with control signals output from generation means to selectively output any of the above data. a selection means for inputting the image data and supplying it to the image memory; A graphic characterized by comprising pixel occlusion in screen display devices. Palation processing equipment. 2. The logic operation means is output from the straight line generation means. The logic corresponding to the input logic operation control signal The above patent claim is for performing scientific operations. The graphic display described in item 1 of the scope of Pixel operation in play equipment tion processing equipment. 3. The selection means is a logical operation with the source data. Calculated data corresponding to the part that has been calculated Output the data, match it to other parts, and display it. Output the stnation data itself Claim 1 Graphic display devices mentioned in section pixel operation processing unit in Place.