JPH10334251A - Fast plotting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain the fast plotting on a graphic screen. SOLUTION: This device has a central arithmetic processing unit 11 and an image memory 17. The pixel data are read out of the memory 17 and an image is plotted on a display 20. A pixel data generation means 18 is added between the unit 11 and the memory 17. Then the unit 11 gives some of pixel data to the means 18. Thus, the means 18 generates the deficient pixel data and repeats an operation to write the deficient pixel data and the pixel data sent from the unit 11 into the memory 17. As a result, an image can be fast drawn on a graphic screen.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed drawing apparatus suitable for use in a field of an automatic drafting apparatus called CAD or the like or a field of computer graphics.

[0002]

2. Description of the Related Art A conventional drawing apparatus will be described with reference to FIG. In the figure, reference numeral 10 denotes a drawing apparatus main body, and reference numeral 20 denotes a display (either a cathode ray display or a liquid crystal display). The drawing apparatus main body 10 is generally constituted by a computer. The schematic configuration of the computer is illustrated by a central processing unit 11, a read-only memory 12, a rewritable memory 13, an input port 14, and an output port 15.

Here, an example is shown in which an XY address generator 16 and an image memory 17 are provided to make a computer function as a drawing device. The image memory 17 is a display 20
Has a storage address corresponding to all the pixels on the display screen, and writes pixel data having an arbitrary color and luminance at an arbitrary address in accordance with an XY address signal generated by an XY address generator 16. it can.

The pixel data written in the image memory 17 is read out and transferred to the display 20, and the pixel data stored in the image memory 17 is displayed on the display 20 as an image. Here, an example of inputting an image will be described. FIG.
In the example shown in FIG. 5, an example is shown in which a line L is drawn between points P1 and P2 on the screen of the display 20. The input port 14 is connected to input means 30 called, for example, a mouse. Input means 30
To display the cursor K on the display 20. The position of the cursor K is managed by the central processing unit 11 according to the XY address generated by the XY address generator 16. That is, the cursor K is positioned at the position P1, and the click operation (operating the switch attached to the mouse) is performed.
Then, the central processing unit 11 reads the XY address of the position P1.

[0005] The cursor K is moved to the position P2 and clicked again to read the XY address of the position P2 into the central processing unit 11. The central processing unit 11 calculates an address of the image memory 17 corresponding to the line connecting the positions P1 and P2, and sequentially writes pixel data having the specified color and luminance at the address.

FIG. 4 shows how pixel data is written to each address of the image memory 17. A1, A2, A3... Indicate addresses at which pixel data is to be written, and W indicates parameters corresponding to the width of the line L to be drawn (preset by the operator). The central processing unit 11 has the positions P1 and P
2 by reading the XY address of
Addresses on a line connecting addresses, for example, A1, A4, A
7, A10 ... are calculated. At the same time, A2 and A3 are added to A1 and A5 and A6 are added to A4 according to the line width W set in advance by the operator, and pixel data is written to each address.

[0007]

Conventionally, an image memory 17 is used.
The operation of writing pixel data to each of the addresses A1, A2, A3. For this reason, the central processing unit 11 executes not only arithmetic processing such as calculating an address corresponding to a line connecting the positions P1 and P2 on the image, but also writing processing of pixel data to each address of the image memory 17. Since it is indispensable, the amount of processing is large, and even if a processor with a high processing speed (central processing unit) is used, the drawing speed on the graphic screen is limited, which is one of the factors that cannot achieve high speed. ing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a high-speed drawing apparatus capable of reducing a processing amount required for writing processing to an image memory of a central processing unit, thereby enabling high-speed drawing.

[0009]

According to the present invention, pixel data generating means is inserted between the central processing unit and the image memory, and the central processing unit is provided with a predetermined number of pixel data generating means (capacity of the buffer memory). (Determined number) of initial addresses (corresponding to, for example, A1, A4, A7, 10... Shown in FIG. 4), line width data, color data, and luminance data. The pixel data generation means calculates an address (corresponding to A2 and A3 for A1) required for a line width following each initial address, generates pixel data to be written to each address, and stores the pixel data in an image memory. Write to.

While the pixel data generating means generates the pixel data and writes it to the image memory, the central processing unit 11 can execute other processing. When the pixel data generating means writes the pixel data into the image memory and the buffer memory becomes empty, the central processing unit again transfers the initial addresses, color data and luminance data determined by the capacity of the buffer to the pixel data generating means. , Pixel data is generated. At the same time, the operation of writing the pixel data to the image memory is repeatedly executed.

Therefore, according to the present invention, the central processing unit only needs to send the initial address and the pixel data stored at the initial address to the pixel data generating means. While the pixel data generating means is writing pixel data to the image memory, the central processing unit 11 can perform other tasks, for example, other tasks necessary for drawing an image. As a result, an advantage that the display speed of an image can be increased is obtained.

[0012]

FIG. 1 shows a schematic configuration of a high-speed drawing apparatus according to the present invention. The feature of the present invention is as follows.
The point is that pixel data generating means 18 is provided between the central processing unit 11 and the image memory 17. The pixel data generating means 18 calculates an address giving a line width following the initial address according to the initial address sent from the central processing unit 11 and the line width data. The initial addresses sent from the central processing unit 11 are A1, A4, A7, A10... Or A2, A5, A8,.
.. Or A3, A6, A9, A12,. The arrangement of the addresses corresponds to the position P shown in FIG.
When the line L connecting 1 and P2 is drawn, the central processing unit 11 calculates by giving the positions P1 and P2.

Here, addresses A1, A4, A7, A1
The description will be made with the arrangement of 0 ... as the initial address. The pixel data generating means 18 receives the initial addresses A1, A4, A7, A10,.
The address matching the line width W (see FIG. 4) following 4, A7, A10... Is calculated. When a line width W of three pixels is given as the line width, for example, as shown in FIG. 4, the pixel data generating means 18 calculates addresses A2 and A3 immediately above the initial address A1. A5 and A6 are used for the initial address A4, and A5 is used for the initial address A7.
8 and A9, and A11 and A for the initial address A10.
12 are calculated respectively. When an address corresponding to the center in the line width direction is taken as the initial address, the upper and lower addresses A1, A3, A4 and A6, A7, A9... Of the initial address at the center are calculated.

Addresses A2 and A following the initial address A1
When 3 is calculated, the pixel data generating means 18 writes the pixel data composed of the color data and the luminance data at the designated address of the pixel memory 17. Pixel data generation means 18
Repeats the operation of calculating an address that gives a line width with respect to the initial address sent from the central processing unit 11, and the operation of writing pixel data to the calculated address.

FIG. 2 shows an example of the internal configuration of the pixel data generating means 18. In the figure, BF indicates a buffer memory. An initial address for giving an array of pixels of a line L to be drawn from the central processing unit 11 to the buffer memory BF,
The color and luminance data to be applied to the line L to be drawn are sent. As the buffer memory BF, for example, a shift register type buffer memory called FIFO or the like can be used. According to the FIFO type buffer memory, reading is performed in the order of writing. Buffer memory B
When F becomes full, the central processing unit 11 detects the state and temporarily stops sending data. As the capacity of the buffer memory BF, for example, the initial address is 256
It is possible to have a capacity to receive the address, and color data and luminance data to be added thereto.

The initial address sent to the buffer memory BF is transferred to the sequence controller SQ, and the sequence controller SQ calculates an address giving a line width W adjacent to the initial address. The address giving the line width calculated by the sequence controller SQ is sent to the image memory 17 together with the initial address, and accesses the image memory 17.

IT indicates a luminance data generator. The luminance data generator IT generates an initial address from the sequence controller SQ, a generation timing of an address giving a subsequent line width, and a luminance data from the color data and luminance data added to each initial address from the buffer memory BF. Then, luminance data is generated at each timing of an initial address and an address giving a subsequent line width. As the luminance data, for example, a weight that gives the highest luminance to the center pixel in the line width direction can be added.

COL indicates a color data generator. The color data generator COL takes in the initial address from the sequence controller SQ and the generation timing of an address that defines the line width following the initial address, and sends the initial address from the buffer memory BF at each generation timing of each address. Import color data Accordingly, the color data generator COL also generates and outputs color data for each of the initial address generation timing, the initial address generation timing, and the subsequent generation timing of the address giving the line width.

The luminance data generator IT and the color data generator COL input the luminance data and the color data to the image data generator VRD, and generate pixel data at each address generation timing. This pixel data is stored in the image memory 17.
Of the sequence controller SQ
Is written to the image memory 17 in accordance with the address signal given by

In this embodiment, when writing pixel data to the image memory 17, the sequence controller SQ
Once reads the storage of the writing address (storage in the image memory 17), and reads the read pixel data AVM.
And the pixel data AVN to be written
And a case in which writing is permitted only when the luminance of the pixel data AVN to be written is higher than that of the stored image data AVM. With this configuration, the next screen can be overlaid on the original screen.

[0021]

As described above, according to the present invention, the provision of the pixel data generating means 18 allows the pixel data generating means 18 to store the pixel data in the image memory 17 in place of the central processing unit 11. Since the writing operation is performed, the central processing unit 11 does not need to execute the processing related to writing to the image memory 17. As a result, processing related to other graphics can be executed, so that an advantage that the image display operation can be speeded up as a whole is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram for explaining an outline of the present invention.

FIG. 2 is a block diagram for explaining an example of an internal configuration of a pixel data generating unit which is a main part of the present invention.

FIG. 3 is a block diagram for explaining a conventional technique.

FIG. 4 is a view for explaining a conventional graphic input method.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Drawing apparatus main body 11 Central processing unit 12 Read-only memory 13 Rewritable memory 14 Input port 15 Output port 16 XY address generator 17 Image memory 18 Pixel data generation means 20 Display 30 Input means

Claims (1)

[Claims] 1. A pixel data is written to an image memory in accordance with an instruction output from a central processing unit, and the pixel data stored in the image memory is read and provided to a display. The image stored in the image memory is displayed on the display. In the image drawing device to be displayed, pixel data generating means is provided between the central processing unit and the image memory, and the central processing unit supplies the pixel data generating unit with an initial address, line width data, luminance data, Color data, the pixel data generation device calculates an address of a pixel adjacent to the initial address according to the initial address and the line width data and corresponding to the line width, and sets the pixel data to be written to each address to the luminance. The pixel data is generated according to data and color data, and the pixel data is written to the address of the image memory. Image drawing device.