JPH0731725B2 - Pixel operation processing device in graphic display device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pixel operation processing device in a graphic display device, and more specifically, to destination data already written in an image memory of the graphic display device. , By performing a logical operation based on the new source data,
The present invention relates to a pixel operation processing device for obtaining image data obtained by synthesizing both data and writing the image data in the image memory again.

<Prior Art> In a conventional graphic display device,
The so-called pixel operation processing operation is performed to superimpose the newly supplied source data on the destination data already written in the image memory and write it again in the image memory. Based on this, it has a function that can be visually displayed by a CRT display device.

In order to perform the above-described pixel operation processing operation, conventionally, the destination data already stored in the image memory is read by the image processing processor and stored in the internal memory of the image processing processor. A necessary logical operation is performed with the source data to be written, and the image data of the operation result is written again in the image memory. And
The rewritten image data is visually displayed on the CRT display device.

Therefore, for example, for the destination data (CD) shown in FIG. 2, the source data (S
When D) is overwritten, it is sufficient to adopt a logical sum as a logical operation, and it is possible to obtain image data in a state where both data are simply overlaid, and the destination data (shown in FIG. 3) When the source data (SD) shown in FIG. 3 is removed from DD), the exclusive OR is adopted as the logical operation, and the state corresponding to the figure area of the source data (SD) is removed. The image data of can be obtained.

<Problems to be Solved by the Invention> In the pixel operation processing device having the above configuration, the destination data read out from the image memory by the image processing processor is temporarily stored in the internal memory of the image processing processor, and the destination data is stored for each pixel. It is necessary to perform a pixel operation process by performing a logical operation, deleting the destination data stored in the image memory at the end of the logical operation, and writing the above operation result in the image memory again. Therefore, there is a problem that the internal memory capacity of the image processing processor necessary to perform the pixel operation must be increased, and the processing capability of the image processing as a whole is reduced.

More specifically, a destination data read operation from the image memory, a logical operation operation in the image processor, and a logical operation result write operation to the image memory are required for each pixel operation, and moreover, for one screen. Memory capacity equivalent to about 1 Mbit
Therefore, it is necessary to equip the internal memory of the image processor with a large-capacity internal memory of about 1 Mbit in order to store one screen of image data.

In addition, since the logical operation must be performed on the image data of about 1 Mbit, the load on the image processing processor increases, and other processing cannot be performed while the logical operation is being performed. turn into. Therefore, the processing capability of the image processing as a whole is reduced.

<Objects of the Invention> The present invention has been made in view of the above problems,
An object of the present invention is to provide a pixel operation processing device capable of performing pixel operation without imposing a burden on the image processing processor.

<Means for Solving the Problems> In order to achieve the above object, a pixel operation processing device in a graphic display device according to the present invention has a logical operation control signal output from a straight line generating means as an input and a logical operation designating signal. For outputting the write mode signal to the image memory with the start signal output from the straight line generating means as an input, the source data output from the straight line generating means, and the read from the image memory. Input destination data to be input, logical operation means for performing a logical operation based on the logical operation designating signal, operation data output from the logical operation means, and destination data read from the image memory, and , The control signal output from the straight line generating means And a selecting means for selectively outputting any one of the above data corresponding to the above and supplying it to the image memory.

The control data output from the straight line generating means is brightness data, and the selecting means outputs the operation data corresponding to the portion subjected to the logical operation with the source data, and corresponds to the other portion. The destination data itself is preferably output.

<Operation> With the pixel operation processing device having the above configuration, the straight line generation means generates a straight line based on the graphic data transmitted from the image processing processor, and the generated straight line is written into the image memory, and the contents of the image memory are written. In a graphic display device that displays images based on
When new source data is written to the destination data already written in the image memory, the source data output from the straight line generating means and the destination data read from the image memory are used as inputs to obtain the logic. The arithmetic means performs a logical operation based on both data, and the arithmetic data output from the logical operation means and the destination data read from the image memory are input to the selection means and correspond to the control signal output from the straight line generation means. Then, by selectively outputting any one of the above-mentioned data by the selecting means and supplying it to the image memory, the image data in which the source data is written in the destination data can be written in the image memory again. .

Further, the control data output from the straight line generating means is brightness data, and the selecting means outputs the operation data corresponding to the portion subjected to the logical operation with the source data and causes the other data to correspond to the other portion. When the destination data itself is output as the destination image data, it is possible to obtain image data in which only the portion of the destination data on which the logical operation is actually performed is replaced with the operation data.

<Example> Hereinafter, detailed description will be given with reference to the accompanying drawings illustrating an example.

FIG. 4 is a block diagram showing an outline of a graphic display device, which includes a host computer (31), a transmission line, and a host interface (32).
Data is transmitted to a graphic data management section (33) that manages a segment buffer (not shown). In the graphic data management section (33), the transmitted data is arranged in a state in which it can be displayed as a graphic, and each graphic data is given an identification number and priority and stored in the segment buffer. Then, the data read from the segment buffer is guided to a data analysis unit (34) for analysis, vector operation processing is performed based on the start point coordinates and the end point coordinates, and the processing result is transferred to the coordinate conversion / clip unit (35). The data is transmitted and multiplied with a matrix corresponding to enlargement, reduction, rotation, translation, etc., and when necessary, the portion protruding from the frame is clipped. Then DDA
The control / filling section (36) creates the data that is the source of the line segment generation, and when the fill is required, the data that is the source of the horizontal line segment generation corresponding to the part to be filled is generated. By supplying the generated data to a straight line generating unit (hereinafter abbreviated as DDA) (37), the coordinates in the middle of the vector connecting the start point coordinates and the end point coordinates are calculated to actually generate a line segment. Then, each dot corresponding to the line segment data actually generated is supplied to the pixel operation processing unit (38), and the image data output from the pixel operation processing unit (38) is stored in the image memory (39). , The data stored in the image memory (39) is read by the video control section (40), and the D / A
Converts into analog signals by converting, and also converts into video signals based on the color conversion table, and then supplies it to the monitor display (41), resulting in figures based on the data transmitted from the host computer (31). Is made visible.

FIG. 1 is a block diagram showing the configuration of the pixel operation processing unit in detail, and has a logical operation circuit (1) and a selector (2) as main parts.

More specifically, the logical operation circuit (1) is
It is possible to select the logical operation to be executed based on the logical operation specifying signal supplied from the outside.
Source data (SD) output from 7) and destination data (DD) read from the image memory (39) are supplied as data to be subjected to logical operation. Then, the logical operation control signal (CS) output from the DDA (37) is converted into a logical operation designation signal (a) by the decoder (3) and supplied to the logical operation circuit (1).

The selector (2) is supplied with the brightness data (ID) output from the DDA (37) as a control signal, and the operation result data (OD) from the logical operation circuit (1), And destination data (DD) read from the image memory (39) is supplied as selected data. The operation result data (OD) is output when the luminance data (ID) is valid, and the destination data (DD) is output when the luminance data (ID) is not valid. The selector (2) is controlled. The output data (WD) from the selector (2) selected as described above is supplied to the image memory (39).

The write timing circuit (4) for supplying the write mode signal (b) to the image memory (39) includes the DDA (3
The start signal (c) output from 7) is supplied. When the write mode signal (b) from the write timing circuit (4) is supplied to the image memory (39), the destination data from the image memory (39) is transferred during the first half of the write cycle. (DD) is output.

The operation of the pixel operation processing device (38) having the above configuration is as follows.

First, the logical operation control signal (CS) is supplied from the DDA (37) to the decoder (3), and the logical operation control signal is decoded in the decoder (3) to specify the logical operation such as logical sum and logical product. The logical operation designating signal (a) is generated and supplied to the logical operation circuit (1) so that a desired logical operation can be performed.

Next, from the DDA (37), the start signal (c) to the write timing circuit (4), the source data (SD) to the logical operation circuit (1), the brightness data (ID) to the selector (2), Supply each.

In this state, since the write mode signal (b) from the write timing circuit (4) is supplied to the image memory (39), the image memory (39) enters the write cycle. Since the destination data (DD) is output in the first half of the cycle, the logical operation circuit (1) receives the source data (SD) and the destination data (DD) as inputs and outputs the logical operation designating signal (a). It is possible to perform the logical operation selected by) and supply the operation result data (OD) to the selector (2).

The destination data (DD) is also supplied to the selector (2). If the luminance data (ID) is valid, the operation result data (OD) is selected and the luminance data (ID) is valid. If not, the destination data (DD) is selected and the data on the selected side is supplied to the image memory (39) as write data (WD). Therefore, in the latter half of the write cycle, the write data (DD) WD) can be written back to the image memory (39).

More specifically, as shown in FIG. 2, the source data (S
When D) is superimposed, the logical operation control signal (CS) output from the DDA (37) may be a signal corresponding to the logical sum, and in the logical operation circuit (1), the destination data ( DD) and source data (SD) can be ORed.

Since the brightness data (ID) is valid only in the figure area (e) of the source data (SD), that is, the area where the figure exists, the logical operation circuit is made to correspond to the figure area (e). The operation result data (OD) output from (1) is supplied to the image memory (39), the destination data (DD) is supplied to the image memory (39) corresponding to the remaining area, and finally, The image memory (39) contains
Source data (SD) to destination data (D
It is possible to write graphic data that is overlaid with D).

Further, as shown in FIG. 3, when the source data (SD) is temporarily erased from the destination data (DD), the logical operation control signal (CS) output from the DDA (37).
Is a signal corresponding to the exclusive OR, and the logical operation circuit (1) can perform the exclusive OR operation of the destination data (DD) and the source data (SD).

Since the brightness data (ID) is valid only in the graphic area (g) of the source data (SD), that is, in the area where the graphic exists, the logical operation circuit is made to correspond to the graphic area (g). The operation result data (OD) output from (1) is supplied to the image memory (39), the destination data (DD) is supplied to the image memory (39) corresponding to the remaining area, and finally, The image memory (39) contains
It is possible to write figure data that is the source data (SD) temporarily erased from the destination data (DD).

In addition, if the figure data temporarily erased as described above is used as the destination data (DD) and the exclusive OR operation is performed again with the source data (SD), the original erased data is eliminated. The destination data (DD) in the state of is obtained.

As is clear from the above description, in the above embodiment, the DDA (3
By the pixel operation processing unit (38) provided between the image data (7) and the image memory (39), the logical operation of the destination data (DD) and the source data (SD), the image data to the image memory (39) Can be rewritten. That is, since the pixel operation processing section (38) is configured by hardware, it is possible to perform pixel operation at high speed without binding the image processor at all.

<Advantages of the Invention> As described above, according to the present invention, a pixel operation can be performed without imposing a burden on an image processor, and further, a logical operation and a writing are performed during a writing cycle to a normal image memory. The unique effect that high-speed drawing processing can be performed due to the fact that it is possible, and further that the processing efficiency of the entire graphic display device can be improved by reducing the load on the image processing processor. Play.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a pixel operation processing device of the present invention, FIGS. 2 and 3 are schematic diagrams showing a concrete example of pixel operation, and FIG. 4 is a schematic diagram of a graphic display device. Block Diagram. (1) …… Logic operation circuit, (2) …… Selector, (3) …… Decoder, (37) …… DDA, (38) …… Pixel operation processing unit, (39) …… Image memory, (DD ) …… Destination data, (SD) …… Source data, (OD) …… Computation result data, (ID) …… Luminance data, (CS) …… Logic operation control signal, (a) …… Logic operation specification signal

Claims (2)

[Claims] 1. A graphic display device for generating a straight line by a straight line generating means based on graphic data transmitted from an image processor, writing the generated straight line in an image memory, and displaying an image based on the contents of the image memory. , A decoding means for outputting a logical operation designating signal with the logical operation control signal output from the straight line generating means as an input, and a write mode signal to the image memory with a start signal output from the straight line generating means as an input A logical operation means for performing a logical operation based on the logical operation designating signal with the write timing means, the source data output from the straight line generating means, and the destination data read from the image memory as input, and the output from the logical operation means. Calculated data, and the data read from the image memory. And a selection means for selectively outputting any one of the above data in response to a control signal output from the straight line generation means and supplying the data to the image memory. A pixel operation processing device in a display device. 2. The control data output from the straight line generating means is brightness data, and the selecting means outputs the operation data corresponding to the portion subjected to the logical operation with the source data,
The pixel operation processing device in the graphic display device according to claim 1, wherein the destination data itself is output in correspondence with another portion.