JPS63308363A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To simplify the process by selectively forming a semiconductor layer on the semiconductor region except the connecting section of a first electric element formed on a semiconductor substrate, and forming a second electric element on the surface of the semiconductor layer, thereby omitting the recrystallization process and the process for exposing the connecting section of the electrode. CONSTITUTION:A semi-insulating GaAs epitaxial layer 9 is selectively grown by a MOVPE method for instance. At this time, since a gate electrode 4, a side wall 6 and an ohmic electrode 8 are small as compared with the respective connecting sections of the gate electrode 4 and the ohmic electrode 8 and an ohmic electrode connecting section 8', they are buried in the semi-insulating GaAs epitaxial layer 9, but conversely, the connecting section of the electrode 8 and the connecting section 8' are not completely buried because of their sizes. Then, as with a Schottky type field effect transistor A, after forming an N-type semiconductor region 10 by a Si ion implantation, a gate electrode 11 and a side wall 12 are provided, and thereafter a N<+> semiconductor region 13 is formed and an ohmic electrode 14 is formed, thereby forming a Schottky type field effect transistor B.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a three-dimensional structure and a method for manufacturing the same.

2. Description of the Related Art A conventional device is shown in FIG. A method of manufacturing the conventional device shown in FIGS. 3a-yf will be described below. As shown in FIG. 3a, an N-type semiconductor region 32 formed on, for example, a semi-insulating GaAs substrate 31 by, for example, ion implantation and annealing is etched using techniques such as vapor deposition, photolithography, and dry etching. w sio
, 6, a +N semiconductor region 34 which becomes an ohmic region is formed using the gate 33 as a mask, and is made of Go, for example, by vapor deposition.
! An ohmic electrode 36 is formed to form a semiconductor element such as a field effect transistor.

Next, on the Gaps substrate 1 including the semiconductor element.

As shown in FIG. 3, a 5rlF2 single crystal 36, which is less likely to react with GaAs than with Ge and has high insulating properties, is grown to a thickness of about 200 nm by molecular beam epitaxy (MBK) or the like. Next, as shown in FIG. 3C, after forming 5i0237 to cover the semiconductor substrate, GaA
Go, which has a lattice constant similar to that of s, is laminated by the MBK method to a thickness of approximately 1 μm as the intermediate layer 38. Since the Ge intermediate layer 38 immediately after lamination is polycrystalline, as shown in FIG. 3d, after depositing a cap layer 39 made of, for example, W on the intermediate layer 38, 5rF236 is seeded by heating, for example, by electron beam annealing. As a result, the intermediate layer 38 is recrystallized together with the Ha on the SiO□3T.

Next, as shown in FIG. 3e, after removing the cap layer 39 by dry etching or the like, a semi-insulating GaAs epitaxial layer 4o is deposited to a thickness of about 1 μm. Next, as shown in FIG. 3e, the semi-insulating GaAs epitaxial layer 40 and the Ge intermediate layer 38 are etched, for example, by dry etching.
is partially opened and G! is selectively applied onto the ohmic region of the semiconductor element. A LAs contact layer 31 is grown.

Finally, as shown in FIG. 3f, in a similar manner to semiconductor devices, such as field effect transistors.

After forming the semiconductor element B, a wiring process is performed to obtain the intended device.

Problems to be Solved by the Invention The following problems arise from the structure and manufacturing method of such a conventional device. Firstly.

Due to surface contamination and poor morphology during the removal of the W cap layer 39 during recrystallization of the Ge intermediate layer 38, semi-insulating GaA! Irregularities and grains occur on the surface of the epitaxial layer 4o. Such irregularities and grains adversely affect the characteristics of the element. Further, during recrystallization, the temperature of the substrate surface rises to about 80° C., so that the characteristics of the semiconductor substrate formed on the semi-insulating GaAs substrate 31 are also deteriorated due to thermal distortion. Therefore, there is a problem that the reproducibility of the device characteristics is poor and the variation is increased. Second, finally, e
The entire process for forming the aAs epitaxial layer 4o is complicated because it includes the formation of the SrF2 single crystal 26, the stacking of the Ge intermediate layer 38, and the accompanying formation of the W cap layer 39. Furthermore, as shown in FIGS. 3e and 3f, the process becomes complicated because a step of forming a contact layer 41 connecting the semiconductor element B and the semiconductor element B is required.

An object of the present invention is to provide a highly integrated semiconductor device that is uniform and reliable, using a simplified process that does not require the complicated steps of conventional devices.

Means for Solving the Problems The present invention provides a method for selectively growing an epitaxial growth layer for forming a second electric element on a region of a semiconductor substrate other than the connecting portions of electrodes constituting the first electric element. The present invention is characterized by a semiconductor device and a method for manufacturing the same.

action The operation of the present invention will be briefly explained.

Epitaxial growth on semiconductor substrates, usually.

Although it is known that MO-C grows on the surface of a semiconductor substrate,
In vapor phase growth methods such as VD, a semiconductor layer grows on a metal or insulating film pattern formed on a semiconductor substrate, depending on the shape and size of the pattern or growth conditions, and embeds the pattern. It has the effect of causing it to disappear. The present invention utilizes this effect.

EXAMPLE Hereinafter, an example of the present invention will be shown in cross-sectional views shown in FIGS. 1a-h, and a manufacturing method thereof will be explained. first.

As shown in FIG. 1a, 4, OX
N-type semiconductor region 3 is formed by implanting Si ions at a sheet carrier concentration of lolm.

Next, as shown in FIG. 1, for example, WSi is deposited by sputtering or the like. After 2000 people deposited a high melting point metal such as No. 6 on the entire surface, it went through two photo-etching and dry-etching steps.
A gate electrode 4 having a gate length of 1 μm is formed. In this example, 5i025 was formed on the gate electrode 4 by 2000 people at the same time.

Next, as shown in FIG.
After depositing 400OA of 5102 using the CVD method, the SiO□ was etched by anisotropic dry etching to a width of 5ooo.
Form the side wall θ of a person.

Next, as shown in FIG. 1d, the gate electrode 4 and the Si
, 02 as a mask, S1 ions with a sheet carrier concentration of 1×10 are implanted at an acceleration voltage of 60 KaV to form an N semiconductor substrate, and annealing is performed at 820° C. for 16 minutes to form an N type semiconductor region 3. and N semiconductor region 7
Activate.

Next, as shown in FIG. 1e, a heat-resistant ohmic electrode 8 made of, for example, Ge or W is formed at a distance of 2/1 m from the side wall 6 and with a length of 2 μm to form a Schottky pear-shaped field effect transistor. establish. Here, 8' is a connection part of an ohmic electrode of 4 μm square.

In this embodiment, a Schottky field effect transistor is used as an example, but the semiconductor element may also be formed using a hetero type transistor or an Ml'S type transistor using the MBX method or the MOVPE method.

In FIG. 1f, semi-insulating Ga, which is a feature of the present invention,
The As epitaxial layer 9 is selectively grown to a thickness of about 17 tm using, for example, the MOVPII method at a substrate temperature of, for example, 600'C. At this time, the gate electrode 4, the side wall 6, and the ohmic electrode 8 are compared with the connection parts of the gate electrode 4 and the ohmic electrode 8, which are not shown in FIG. 1, and the ohmic electrode connection part 8' shown in FIG. Since it is small, it is embedded in the semi-insulating GaAs epitaxial layer 9, but on the contrary,
The connection portion of the electrode 8 and the connection portion 8' are not completely embedded due to their size. In this embodiment, for example, the ohmic electrode 8 and its connection portion 8' have the same thickness, but only the connection portion 8' may be made thicker and buried.

Another embodiment of the present invention is also shown in FIG.

For example, on the GaAs substrate 23, a stripe pattern 21 that forms an angle of 30° with respect to the (110) plane is easily embedded, whereas patterns that are at other angles, such as oo or 9000 angle, are difficult to be embedded. The connection portions 22 are patterned in a direction that brings out the above characteristics to provide selectivity. 24 is semi-insulating GaAs
It is an epitaxial layer.

In addition to the above Ga5S epitaxial layer 9.24,
A heteroepitaxial layer made of GaAs or MuS, a P-type G&S to which impurities are added, or a multilayer epitaxial layer made of a combination of these materials may be used.

Next, as shown in FIG.
After forming the N-type semiconductor region 10 at a temperature of 60 KaV 1.6×1012, the gate electrode 11 and sidewalls 12 are provided, and then the N+ semiconductor region 13 is formed at a temperature of 60 KaV 1. OXI
Formed under the conditions of ``Q13cm''.

After annealing, an ohmic electrode 14 made of, for example, MuGe is formed by vapor deposition to form a Schottky field effect transistor B. In addition to the Schottky field effect transistor B, transistors such as hetero-type transistors and MIS-type transistors, and resistor elements such as resistors may also be formed.

Finally, as shown in the first diagram, a wiring 16 is provided to the ohmic electrode connection portion 8' to obtain a semiconductor device which is an object of the present invention.

In addition to the effects of the invention, the present invention selectively utilizes epitaxial growth in a three-dimensional semiconductor device to eliminate the recrystallization process of the grown layer and the process of exposing the connection part of the electrode. This simplifies the process, thereby improving element reproducibility and reducing variations, thereby providing a highly reliable and highly integrated semiconductor device.

[Brief explanation of drawings]

1a-h are process cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2a is a plan view showing an electrode pattern in a device according to another embodiment of the present invention, and FIG. b-d are process cross-sectional views of the example at the same location, Figure 3 a-f'
1A and 1B are process cross-sectional views showing a conventional method for manufacturing a semiconductor device. 1.23... Semi-insulating GaAs substrate, 2...
...Resist, 3,10...N-type semiconductor region, 4.11...Gate electrode, 6...5
i02, 6, 12...Side wall, 7.13...
...N Semiconductor region, 8.14...Ohmic electrode, 8'...Ohmic electrode connection part, 9
．． 24... Semi-insulating Ga1a epitaxial layer, 1θ... Wiring, 21... Stripe pattern, 22... Connection portion. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 cL58-Ql.

Claims (2)

[Claims] (1) A semiconductor layer is selectively formed on a semiconductor substrate region excluding a connection portion of an electrode of a first electric element formed on a semiconductor substrate, and a second electric element is formed on the surface of this semiconductor layer. A semiconductor device. (2) On a semiconductor substrate, the direction of a strip-shaped electrode constituting an electric element and the direction of a rectangular connection portion connected to the strip-shaped electrode are formed to be different with respect to a specific surface orientation of the semiconductor substrate. A method for manufacturing a semiconductor device, in which a semiconductor layer is selectively grown.