JPS63304741A - Bus right arbiter circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution and to attain short time access by providing a requester sending a bus right request signal to an arbiter arbitrating the bus right of the system so as to arbitrate the bus right of on internal bus. CONSTITUTION:When a master/slave 11(M3) generates a transfer request (at this point of time, access to a bus (b) or (c) is not clear), a bus right request signal is given to an arbiter CO of a system bus 1 via a requester 14 in a card C3. When a bus right of a system bus 1 is recognized in the M3, the requester 14 of the card C3 occupies the system bus 1 after the present bus cycle is finished. Then the M3 uses the internal bus B3 to start the actual access. When it is an access to the bus (b), the system bus 1 is being occupied, and if the access is directed to the bus (c), the system bus 1 is released. The distinguishment between the buses (b) and (c) is implemented by a decoder 13 and it is delivered to the requester 14. Thus, the circuit constitution is simplified and the access time is decreased.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides the exclusive right (
This invention relates to an improvement of a bus right arbitration circuit that determines the bus right (hereinafter referred to as bus right).

[Prior Art vII] Information transfer operations on a bus forming a part of a microprocessor device are important factors in determining the performance of the device.

Information transfer between each functional block constituting a device varies, such as those that require an average transfer speed, those that may require a slow transfer speed, and those that require high-speed transfer with a low transfer frequency.

A bus arbitration circuit is used to arbitrate these various transfers. The bus right arbitration circuit grants bus rights to a plurality of cards connected to the system bus that can serve as bus masters, based on a predetermined bus use priority order.

Conventionally, there has been a bus arbitration circuit having the configuration shown in FIG. 2, for example.

In the figure, 1 is a system bus to which a plurality of cards 01 to C3 are connected, through which address signals, data signals, control signals, etc. are transmitted. Cards C1 to C3 are cards that can serve as bus masters.

Reference numeral 2 denotes an arbitration bus to which an arbiter CO is connected, through which arbitration signals are transmitted. Arbiter CO arbitrates for bus rights to system bus 1.

The cards C1 to C3 are provided with a master 3 and slaves 4 to 6 subordinate thereto.

7.8.9 is the internal bus B1. of cards C1, C2, C3.
82. This is a bus interface (hereinafter referred to as bus I/F) through which signals transmitted between B3 and system bus 1 pass.

Reference numeral 10 denotes an arbiter that arbitrates for bus ownership of the internal bus B3. The master/slave 11 (hereinafter referred to as M3) is a device that has a register that is set by an external signal and can also serve as a mask, such as D
MAC (Direct Memory Access Controller)
It is.

Reference numeral 12 denotes a requester that sends a bus request signal to the arbiter CO via the arbitration bus 2 when the card C3 wants to obtain the bus right. Reference numeral 13 denotes a decoder that decodes the signal on the internal bus B3 and transmits it to the requester 12.

In such a bus right arbitration circuit, a card that wants to use the system bus 1 requests the bus right from the arbiter CO via the arbitration bus 2, and after receiving permission, performs actual bus access.

Now, consider three accesses a, b, and c shown in FIG. No two of these accesses can be performed at the same time.

Accesses b and C are both cycles executed with M3 as a mask, but in access b, system bus 1
The difference is that access by C requires bus authority, whereas access by C does not require it.

Since accesses b and C are distinguished based on the address output by M3, it is not known whether system bus 1 is required until M3 takes control of internal bus B3 of card C3. In other words, if you want to request bus rights to system bus 1 for access to b, you must first use internal bus B3.

On the other hand, access of a is B1.1. Use bus B3.

Since the access of a and the transfer request of M3 are completely asynchronous, an arbiter 10 is provided to avoid signal 9 collision on the internal bus B3.

The arbiter 10 performs arbitration under the following conditions.

When 0M3 is using internal bus B3, for example when accessing C, M3 sends the OWN signal to bus E/F9.
to disconnect card C3 from system bus 1, and
Prohibit access to.

(2) If a transfer request for M3 occurs during the access of a, M3 is not given bus rights to the internal bus B3 until the access of a is completed.

[Problems to be Solved by the Invention] However, in such a bus arbitration circuit, each card has its own arbiter, and two-stage arbitration is performed between the external arbiter CO and the card's internal arbiter. There are problems in that the circuit configuration becomes complicated and the time from when a transfer request is made to when access becomes possible becomes long.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to realize a bus arbitration circuit that has a simple circuit configuration and can be accessed in a short time after a card issues a transfer request. purpose.

[Means for Solving the Problems] The present invention provides a bus rights arbitration circuit that grants bus rights to a plurality of cards connected to a system bus that can serve as bus masks, based on a predetermined priority order of bus usage layers. , is connected to the internal bus of the card 1, and when a device that can serve as a bus mask for this internal bus generates a transfer request, it sends a bus request signal to the arbiter that arbitrates for the bus right of the system bus. A bus rights arbitration circuit is characterized in that it is provided with a requester that arbitrates bus rights.

[Example code] Hereinafter, the present invention will be explained using the drawings.

FIG. 1 is a block diagram of an embodiment of a bus arbitration circuit according to the present invention. Components in FIG. 1 that are the same as those in FIG. 2 are given the same reference numerals.

The bus arbitration circuit shown in FIG. 1 has no arbiter in the card C3, and a bus request signal from M3.

The difference from the circuit shown in FIG. 2 is that the signal is provided to the arbiter CO via the requester 14. Similar to the circuit shown in FIG. 2, access to a is prohibited while M3 is using internal bus B3. M3 is a type of device that generates a bus request signal and, after receiving permission for the signal, performs the actual cycle.

In such a bus arbitration circuit, when M3 issues a transfer request (at this point, it is unknown whether the access is B or C).
, a bus request signal is given to the arbiter CO of the system bus 1 via the requester 14 in the card C3.

When M3 is granted bus ownership of system bus 1, requester 14 of card C3 occupies system bus 1 at the end of the current bus cycle.

M3 then starts the actual access using internal bus B3. If it is an access by b, it continues to occupy system bus 1, and if it is an access by C,
Free system bus 1.

The decoder 13 distinguishes between access b and access C, and notifies the requester 14 of the distinction.

[Effects] According to the present invention, the card C3 uses the internal bus B3 after occupying the system bus 1, so there is no conflict between the access of a and the transfer request of M3. Therefore, since there is no need to perform arbitration at the entrance of the card C3, there is no need to provide an arbiter within the card C3. This simplifies the circuit configuration. Furthermore, since arbitration only needs to be performed once, the time from when M3 issues a transfer request to when it actually accesses is shortened.

In such a circuit, the performance of the system will not deteriorate unless the frequency of access to C, which is not actually used even though the bus right of system bus 1 is reserved, increases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a bus right arbitration circuit according to the present invention, and FIG. 2' is a block diagram of a conventional example of a bus right arbitration circuit. 1...System bus, 2...Arbitration bus, 3...Mask, 4-6...Slave, 11...Master/slave, 14...Requester, 81-B3...Internal bus , CO...arbiter, C1-C3...card.

Claims (1)

[Claims] A bus arbitration circuit that is connected to an internal bus of a card and that grants bus rights to a plurality of cards that are connected to a system bus and that can serve as bus masters based on a predetermined bus usage priority order. and a requester that sends a bus request signal to an arbiter that arbitrates the bus rights of the system bus to arbitrate the bus rights of the internal bus when a device that can become a bus master of the internal bus generates a transfer request. A bus right arbitration circuit characterized by: