JPH04328663A - Method and device for dram access arbitration - Google Patents

Abstract

PURPOSE:To attain a DRAM (dynamic random access memory) access arbitrating method/device which can shorten the total access time when both synchronous and asynchronous bus masters have the simultaneous accesses to the DRAM. CONSTITUTION:A bus access arbiter 3 identifies whether the bus master that has an access request to a DRAM 5 is identical with an asynchronous bus master 2 which can have an access to the DRAM 5 only in a high speed mode or a synchronous bus master 1 which can have an access to the DRAM 5 only in a normal mode. When the bus master 2 is identified, the arbitration is carried out so that an access is possible to the DRAM 5 in a high speed mode. When the bus master 1 is identified, the arbitration is carried out so as to give the access right only in a normal mode so that the access cycle time of the decided fixed length is secured.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a dynamic random access memory (DRAM) that reduces overall access time when a synchronous bus master and an asynchronous bus master are used as bus masters to access the DRAM (dynamic random access memory). The present invention relates to an access arbitration method and device.

0002

2. Description of the Related Art Bus masters (e.g., CPUs (central processing units), DMA transfer controllers (DMA) that access memory)
There are two types of cess): synchronous and asynchronous. A synchronous bus master has a fixed length of time for accessing the memory and reading data, that is, the access cycle time. In the asynchronous bus master, the access cycle time continues until there is a response indicating that the required operation has been completed, and the access cycle time is not a fixed length but a variable length.

There is a DRAM access arbitration device that is connected to a DRAM so that the above-described synchronous bus master or asynchronous bus master can access the DRAM. FIG. 3 shows an example of such a DRAM access arbitration device. Figure 3
, 1 is a synchronous bus master, 2 is an asynchronous bus master, 3 is a bus access arbitrator, 4 is a DRAM controller, and 5 is a DRAM (dynamic random access memory).

[0004] When the synchronous bus master 1 or the asynchronous bus master 2 attempts to access the DRAM 5, it is first necessary to obtain access rights. The access right is granted by a bus request signal (B.RE) to the bus access arbitrator 3.
Q) and receives a bus acknowledge signal (B.ACK) from the bus access arbitrator 3. After that, send the address you want to access.

[0005] Then, from the bus access arbitrator 3 to the DRA
A strobe signal and an address for accessing the DRAM 5 are sent to the M controller 4. D.R.
The following signals are sent from the AM controller 4 to the DRAM 5. The RAS signal (Row Address) indicates that the address value in the row direction (for example, the coordinate value in the X-axis direction) of the memory location that you want to access has been sent.
ss Strobe), and a CAS signal (Column Address Strobe) that indicates that a signal of an address value in the column direction (for example, a coordinate value in the Y-axis direction) has been sent.
robe), control signal, and address (value)
etc. When the access is completed, an acknowledge signal AC is sent from the DRAM controller 4 to the bus access arbitrator 3.
K is issued.

By the way, the conventional DRAM access arbitration method in the bus access arbitration device 3 does not distinguish whether the access is made by the synchronous bus master 1 or the asynchronous bus master 2; Even in this case, a method has been adopted in which a fixed length access cycle time required by the synchronous bus master 1 is allocated for access.

The reason for this is that the asynchronous bus master 2 can operate according to the given access cycle time, so it can operate even if a fixed length of time is allocated. This is because the latter requires a fixed length access cycle time. Since arbitration was not performed by distinguishing between synchronous bus master 1 and asynchronous bus master 2, even if synchronous bus master 1 accessed, the operation would be different. It must be possible to do so without any hindrance. Therefore, the bus access arbitrator 3 has always been operated by allocating a fixed length of access cycle time.

[0008]

Problem to be Solved by the Invention (Problem) However, in the conventional DRAM access arbitration method described above,
There is a problem in that it is not possible to access the RAM in high-speed mode, and it is not possible to increase the speed of access.

(Explanation of Problem) In general, in addition to the normal access method (normal mode), there are other methods of accessing DRAM (access mode) such as ``high-speed page mode'' and ``static column mode.''
It is known that there are high-speed access methods (high-speed modes) such as c Column Mode).

For example, after first specifying address values in the row and column directions to access a certain memory location (access in normal mode), the address values in the column direction are fixed while the address values in the row direction are fixed. This is a method of accessing by changing address values one after another. With this method, there is no need to take the time to newly specify the address value in the row direction, so access can be performed in an extremely short time (shorter than the fixed-length access cycle time for a synchronous bus master). , allowing high-speed access.

[0011] However, although it is possible to access DRAM at high speed as described above, if there are synchronous bus masters connected to the bus access arbitrator, As mentioned above, access can only be made within the fixed length access cycle time determined by the synchronous bus master. Therefore, the high-speed mode could not be utilized, and it was not possible to achieve high-speed access.

The object of the present invention is to solve the above-mentioned problems.

[0013]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a DRA that can be accessed in high-speed mode.
In the DRAM access arbitration method when accessing M from a synchronous bus master and an asynchronous bus master, the synchronous bus master can acquire access rights to the DRAM.
We decided to do this only when the access mode is normal mode.

Further, the DRAM access arbitration device is connected to a synchronous bus master and an asynchronous bus master that access a DRAM that can be accessed in a high-speed mode, and a bus master identification signal indicating which bus master has made an access request is transmitted to the DRAM access arbitration device. A bus access arbiter that sends data to the DRAM controller and arbitrates so that the synchronous bus master can acquire access rights only in normal mode, and a bus access arbiter that arbitrates so that the DRAM access mode is set to high-speed mode. The configuration includes at least a DRAM controller that issues an access mode signal indicating whether the mode is normal mode or normal mode.

[0015]

[Operation] The bus access arbitrator determines whether the bus master requesting access to DRAM is an asynchronous bus master that can access in high-speed mode or a synchronous bus master that can only access in normal mode. identify When it is an asynchronous bus master, it arbitrates so that it can access in high-speed mode, and when it is a synchronous bus master, it does not grant access rights unless it is in normal mode so that a specified fixed length access cycle time can be secured. Mediate accordingly. As a result, access from the asynchronous bus master can be performed in high-speed mode, making it possible to shorten the access time as a whole.

[0016]

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a DRAM access arbitration device implementing the DRAM access arbitration method of the present invention. The symbols correspond to those in FIG. The operation of each component is almost the same as the conventional one, but differs in the following points.

The first difference from the conventional method is that the bus access arbitrator 3 identifies whether the synchronous bus master 1 or the asynchronous bus master 2 is attempting to access the DRAM controller 4. The point is that a "bus master identification signal" is sent to the bus master.

The second point is that the "access mode signal" indicating whether the DRAM 5 is currently accessed in normal mode or high speed mode is
The difference is that the data is sent from the DRAM controller 4 to the bus access arbitrator 3.

The third point is that the synchronous bus master 1 can acquire the access right only when the access mode signal is a normal mode signal. (On the other hand, the asynchronous bus master 2 is assumed to be able to obtain access rights without being bound by such conditions.)

In this way, the synchronous bus master 1 can access only in the normal mode, and at this time, a fixed length access cycle time is allocated so that the access operation of the synchronous bus master 1 is not hindered. do. However, if it is determined from the bus master identification signal that the access is from asynchronous bus master 2, the access may be performed in high speed mode. Access time is reduced compared to when executed in normal mode.

FIG. 2 is a waveform diagram illustrating the operation of the DRAM access arbitration device of FIG. 1. This waveform diagram is (1)
First, the asynchronous bus master 2 issues a bus request signal and acquires the access right, accesses the DRAM 5 in high-speed mode, and (2) during the access,
FIG. 4 is a waveform diagram in the case of an example in which the synchronous bus master 1 issues a bus request signal, and when the mode shifts to the normal mode, access rights are granted and access is performed.

As shown in FIG. 2(C), after the asynchronous bus master 2 outputs a bus request signal as shown in ■,
As shown in FIG. 2(d), when the bus access arbitrator 3 outputs a bus acknowledge signal as shown in (3), the asynchronous bus master 2 obtains the access right. Bus access arbitration machine 3
detects that the access is from the asynchronous bus master 2, and sends a bus master identification signal to that effect to the DRAM controller 4 as shown in FIG. Send strobe signal.

If the access by the asynchronous bus master 2 is to be performed in the high-speed mode at this time, as shown in FIG. Sent to machine 3. The end of the access is notified by the output of an acknowledge signal from the DRAM controller 4 as shown in (2), as shown in FIG. 2(H).

In response to the acknowledge signal (■), the strobe signal in FIG. 2 (F) returns to high as shown in ■, and the bus acknowledge signal in FIG. ) bus request signal returns to high as in ■. Further, in response to the strobe signal returning to high as shown in ■, the acknowledge signal in FIG. 2 (h) returns to high as shown in ■.

By the way, even if a bus request signal is issued from the synchronous bus master 1 as shown in (2) in FIG. 2(a), if the asynchronous bus master 2 is accessing, the access right will not be granted, as a matter of course. However, even if the access by the asynchronous bus master 2 is completed and an acknowledge signal is issued from the DRAM controller 4 as shown in FIG. Since the arbitration method is used in which the access right is not granted to the expression bus master 1, the access right cannot be obtained yet even at the point (2).

[0026] The bus access arbitrator 3 performs
Since we have always known that the bus request signal has been issued from the synchronous bus master 1, we receive the signal (■) indicating that the access from the asynchronous bus master 2 has been completed, and send the bus master identification signal to the host in Figure 2. ), the signal is switched to a signal indicating that an access is coming from the synchronous bus master 1.

[0027] As a result, the procedure for shifting the access mode from the high-speed mode to the normal mode is performed, and the procedure shown in Fig. 2 (T) is performed.
In step (10), the mode is shifted to normal mode. As is well known, it takes some time to shift the access mode of the DRAM from the high-speed mode to the normal mode, so it takes some time from point (2) to point (10).

Since the present invention stipulates that the synchronous bus master 1 can acquire the access right only after being placed in the normal mode, as shown in FIG. At time 11), a bus acknowledge signal is issued to the synchronous bus master 1, and the access right is finally acquired. From that point on, the synchronous bus master 1
Access is performed with a predetermined fixed length access cycle time.

Access to the DRAM 5 by the asynchronous bus master 2 and the synchronous bus master 1 is performed as described above, so that access from the asynchronous bus master 2 can be performed even in high-speed mode, and when viewed as a whole, Access is accelerated.

[0030]

As described above, according to the DRAM access arbitration method and device of the present invention, access can be performed in high-speed mode when accessed from an asynchronous bus master, so access can only be made in normal mode. Compared to the conventional example, in which there was no access time, the access time can be shortened as a whole.

[Brief explanation of drawings]

[Fig. 1] DRAM access arbitration device implementing the DRAM access arbitration method of the present invention

[Figure 2] Waveform diagram explaining the operation of the DRAM access arbitration device in Figure 1

[Figure 3] DRAM access arbitration device implementing the conventional DRAM access arbitration method

[Explanation of symbols]

1...Synchronous bus master, 2...Asynchronous bus master, 3...
Bus access arbitrator, 4...DRAM controller, 5...
DRAM

Claims (2)

[Claims] [Claim 1] DR that can be accessed in high-speed mode
In a DRAM access arbitration method when accessing AM from a synchronous bus master and an asynchronous bus master,
DRA is where the synchronous bus master can obtain access rights.
A DRAM access arbitration method characterized in that the method is used only when the access mode to M is normal mode. [Claim 2] DR that can be accessed in high-speed mode
A synchronous bus master and an asynchronous bus master accessing the AM are connected, and a bus master identification signal indicating which bus master has made an access request is sent to the DRA.
A bus access arbiter that arbitrates so that the synchronous bus master can only obtain access rights in the normal mode, and a bus access arbiter that sends the data to the M controller and sets the DRAM access mode to the high-speed mode. A DRAM access arbitration device comprising at least a DRAM controller that issues an access mode signal indicating whether the mode is normal mode or normal mode.