JPS63300682A - Skew compensation circuit - Google Patents

Abstract

PURPOSE:To attain effective suppression of a flicker by converting a bias level of a 1/2 horizontal scanning period delay signal based on a level difference detection result between a 1/2 horizontal scanning period delay signal and a through-signal with respect to a test signal. CONSTITUTION:A test signal outputted from a test signal generator 41 is subjected to noise elimination by an LPF 42 and a switch 43 is connected to the position of a test signal. The test signal biased to a constant voltage by clamp circuits 13, 14 is sent to switches 31, 32, charged in sampling capacitors 52, 54, only a difference voltage is amplified by a 2nd differential amplifier 34 and inputted to a LPF 36. The LPF 36 eliminates a high frequency component from the input signal, sends the result to a bias circuit 37, where the bias voltage of a 1/2H delay line 11 is changed by the signal fluctuation only. Thus, each charge voltage of capacitors 52, 54 is controlled to be equipotential and the output level of the clamp circuits 13, 14 is made coincident and the flicker is suppressed effectively in all levels.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a skew compensation circuit in, for example, a still video (SV) playback device, and in particular to a skew compensation circuit that can effectively suppress flicker during field playback. It is related to circuits.

[Prior art I Sv device's skew compensation circuit prevents distortion from appearing on the reproduced screen when field-recorded image information is displayed on a CRT, for example. This means that one track of the recording medium in Sv includes one field (262,5
Only one piece of information is recorded, and normally this is repeatedly reproduced and supplied to the CRT reproduction device as one screen's worth of information. One frame consists of a combination of an even number field and an odd number field, and the timing of the synchronization signal between the two fields is shifted by a %H (horizontal scanning) period. Therefore, in the skew compensation circuit, one of the reproduction signals for one field is delayed by a period of y2H, the other is left as is, and these are switched every 1 (vertical scanning) period and supplied to the CRT reproduction device.

FIG. 7 shows an example of such a skew compensation circuit. In FIG. 7, 11 is a %H delay line, and the reproduced signal (
(playback signal from the recording medium) is delayed by the HH period. 12
is an automatic gain control (AGC) circuit, and the %H delay line 1
The signal from 1 is amplified with a predetermined gain. The gain of this GG circuit 12 is controlled by an external control signal.

A first clamp circuit 13 inputs a signal from the AGC circuit 12 via a capacitor C1, and clamps the signal to a predetermined level at a predetermined timing in accordance with an external timing signal. Reference numeral 14 denotes a second clamp circuit, which manually inputs the reproduced signal via a capacitor C2, and clamps the human input signal to a predetermined level at a predetermined timing using a predetermined timing signal.

15 and 16 are first and second peak hold circuits, and first and second clamp circuits 13 and 14
The peak level of each signal is held and output. 1
A comparator 7 inputs the signals from the two peak hold circuits 15 and 11i, and outputs the difference signal to the low pass filter (LPF) 18. This LP
The signal input to F18 is band-limited here and input to the GC circuit 12 as a gain control signal.

20 is a switching circuit, which is a PG for SV recording medium.
Based on the PG detection signal from the detection circuit (not shown),
The signals from the two clamp circuits 13 and 14 are selected and output by switching over every one period. Reference numeral 21 denotes a synchronization signal separation circuit which separates a synchronization signal from the output signal from the switching circuit 20 and inputs it to the pulse generation circuit 22.

In the pulse generation circuit 22, the synchronization signal separation circuit 21
A timing (pulse) signal is provided to the first and second clamp circuits 13, 14 based on the timing of the sync chip or hack pouch of the signal from the sync chip or hack pouch.

With the above configuration, skew compensation of the reproduced signal for one field from one track of the recording medium is achieved. Furthermore, flickering on the playback screen is suppressed. That is, within one frame, the level of the signal from the first clamp circuit 13 and the level of the second clamp circuit 14
If the level of the signal from Therefore, two peak hold circuits 1
5.16, the peak levels of the signals from the two clamp circuits 13 and 14 are held, the difference between these two peak levels is determined by the comparator 17, and the output of this comparator 17 is used to eliminate the difference via the LPF 18. The gain of the AGC circuit 12 is controlled as follows. By doing this, flickering on the playback screen is suppressed.

[Problems to be Solved by the Invention] However, in the skew compensation circuit as described above, in order to prevent flicker, the upper end of the signal level (peak level) with respect to the %H delay signal processing system and the through signal processing system. Only the lower end (sync chip or back porch) is used as information for gain control of the circuit 12. Therefore, if the human output characteristics of the y2H delay line 11 are non-linear (the gain differs depending on the DC level of the human input signal), for example, on the playback screen, there will be flicker between bright and dark areas. At the point in the intermediate tone (level) where suppression is effectively performed, there is a difference between the level of the %H delayed signal and the level of the through signal due to the non-linear human output characteristics of the %H delay line 11. Therefore, flicker occurs on the playback screen of the output signal of the switching circuit 20.
The problem was that it could not be effectively suppressed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a skew compensation circuit that solves the above-mentioned problems in the skew compensation circuit and is capable of reproducing a reproduction signal from a recording medium in, for example, Sv while effectively suppressing flicker. It's about doing.

[Means for Solving the Problems] The present invention provides a test signal generating means for generating a test signal, and a level difference between a 1/2 horizontal scanning period delayed signal and a through signal for the test signal from this generating means. 1/2 based on the detection means to be detected and the detection result of the detection means
and means for changing the bias level of the horizontal scanning period delay signal.

[Function 1] According to the invention, the level difference between the 1/2 horizontal scanning period delayed signal and the through signal is detected for the test signal at the intermediate level between the crumble hell and the peak level, and based on the detection result, 1 /2 Change the bias level of the horizontal scanning period delay signal.

[Embodiment 1 FIG. 1 shows an embodiment of the tree invention. In Figure 1, 4
Reference numeral 3 is a changeover switch, and one input terminal inputs a reproduction signal from the recording medium, and the other input terminal inputs a signal from the LPF 42. The switch 43 is controlled by a signal from the test signal generator 41. 11 is %
H delay line (for example, a CCD delay line) which inputs the signal from the output of switch 43 through capacitor C3. 37 is a bias circuit that controls the bias voltage of the y2H delay line 11 based on a signal inputted manually via the LPF 36. FIG. 5 shows an example of the human bias-output level characteristic of the 1/2 H delay line 11.

A first clamp circuit 13 inputs the signal from the %H delay line 11 via the AGC circuit 12 and the capacitor C1. A second clamp circuit 14 inputs a signal from the output terminal of the switch 43 via a capacitor C2.

30 is a pulse generation circuit, and a synchronization signal separation circuit 21
A timing (pulse) signal is manually input to the clamp circuits 13 and 14 at the timing of the sync chip or hack pouch of the synchronization signal from. The clamp circuit 13, Ill, uses a signal from the pulse generation circuit 30 to close the capacitor C.
1, clamps the signal input via C2 to a predetermined level. The output signals from the clamp circuits 13 , 14 are applied to the input terminals of the first and second changeover switches 31 and 32 and to the changeover circuit 20 . As shown in FIG. 2, when the pulse generation circuit 30 receives the vertical synchronization signal of the composite synchronization signal (C-sync) from the synchronization signal separation circuit 21, the pulse generation circuit 30 outputs a horizontal synchronization signal (C-sync). −
L, the α signal, β signal, and a clock (for example, 14 MHz) that are high during the 8H period from the IOH are inputted to the test signal generator 41.

The switching circuit 20 detects PG from a PG detection circuit (not shown).
Based on the detection signal, the signals from the two clamp circuits 13 and 14 are switched and selected every 1V period and output.

Reference numeral 21 denotes a synchronization signal separation circuit which separates a synchronization signal from the output signal from the switching circuit 20 and inputs it to the pulse generation circuit 30.

Based on the synchronization signal (C-sync) as shown in FIG. 2 from the pulse generation circuit 30, the test signal generator 41 generates a test signal as shown in FIG. 181 (generated over several H intervals during the latter half), and inputs power to the LPF 42, and switches the output end of the switch 43 during the same number H intervals. Inside, the switches 31 and 32 are controlled as follows.

That is, the signal from the first clamp circuit 13 is input to the input terminal of the first changeover switch 31, and one output terminal of the switch 31 is connected to the inverting input terminal of the first differential amplifier 33. The other output terminal of 31 is the second differential amplifier 3
Connect to the inverting input terminal of 4. A signal from the second clamp circuit 14 is input to the input terminal of the second changeover switch 32, and one output terminal of the switch 32 is connected to the non-inverting input terminal of the first differential amplifier 33. The other output terminal is connected to the non-inverting input terminal of the second differential amplifier 34. 51.
52, 53, and 54 are capacitors connected to each input terminal of the two differential amplifiers for sampling and holding human input signals. The output signal of the first differential amplifier 33 is transmitted through the first LPF.
35 to the gain control terminal of the AGC circuit 12. The output signal of the second differential amplifier 34 is input to the bias circuit 37 via the 21st PF 36.

One output end of the first changeover switch 31 and one output end of the second changeover switch 32 are set to the 1 channel (C)l) side, and the other output ends of the switches 31 and 32 are set to the 2CH side.

The test signal generator 41 uses the α signal and β signal from the pulse generation circuit 30 to generate a second switching signal with switching timing as shown in FIG. Switch as follows. That is, the second switching signal sets the switch 43 to the reproduction signal side at the low side, and sets the switch 43 to the LPF 42 at the high side.
switch to the side. Further, the test signal generator 41 generates a test signal as shown in FIG. 3 using the β signal from the pulse generation circuit 30 and the clock, and inputs the test signal to the LPF 42. As a method of generating this test signal, a base wall voltage source is provided inside the test signal generator 41, a clock is counted starting from the β signal (for example, every 2n=128 pulses), and the voltage is increased based on this count value. The first level (white 50% level) and second level (white 100% level) signals may be selectively output from the source.
There is no need for the level to be accurate; there is no problem even if the level is within ±10%). Further, in synchronization with the test signal from the test signal generator 41, it becomes low for a sufficiently long time within the range of the white 50% level, becomes high for a sufficiently long time within the range of the white 100% level, and other At the location, a first switching signal having an intermediate level (high impedance) is generated, and thereby the two changeover switches 31J2 are controlled as follows. That is, switch 3
1.32 is set to the IC)l side when the first switching signal is high, set to the 2C)l side when the first switching signal is low, and opened (that is, neither the ICH side nor the 2CH side) when the same signal is at an intermediate level.

Therefore, in the above configuration, during the test signal generation period (from 10H after the vertical synchronization signal generation time)
The period after 8H) operates as follows. That is, the test signal output from the test signal generator 41 is L.
The signal is input to the PF 42, noises such as whiskers and clocks are removed, and the signal is sent to the switch 43. On the other hand, the test signal generator 41 outputs a second switching signal, thereby connecting the switch 43 to the test signal side. The test signal led to the output terminal of the switch 43 is connected to the bias circuit 37 on one side.
The bias voltage set by 1/2H delay line 11
The amplitude level is controlled by the ○C circuit 12, and the sync tip level is fixed at a predetermined level by the first clamp circuit 13. The other test signal is input to the second clamp circuit 14, where the sync tip level is fixed at the same level as the first clamp circuit 13. Each test signal, biased to a constant voltage by two clamp circuits 13.14, is sent to each input of two switches 31.32.

Each test signal sent to each input end of the two switches 31 and 32 is charged to two sampling capacitors 52 and 54 connected to the 2CH side when the white level is 50%, and the two charged signals are Second differential amplifier 3
4, the voltage is amplified by the voltage difference, for example, about 26 dB, and then input to the LPF 36.

The LPF 36 removes high frequency components from the human input signal and sends the signal to the bias circuit 37. Bias circuit 37 is LPF
The bias voltage of the 1/2H delay line 11 is changed by the amount of variation in the signal from 36. In other words, sampling capacitor 5
If it is higher than the charge voltage of the sampling capacitor 54, the bias voltage is lowered, and if it is lower than the charge voltage of the sampling capacitor 54, the bias voltage is increased. In this way, the charging voltages of the two sampling capacitors 52 and 54 are controlled to have the same potential, and the output levels of the two clamp circuits 13 and 14 match. For example, the fact that the charging voltage of the sampling capacitor 52 is higher than the charging voltage of the capacitor 54 means that (a
This is because after a signal such as the human waveform shown in ) passes through the 1/2H delay line 11 and the AGC circuit 12, its upper end is compressed as shown in FIG. This is because, as mentioned above, the bias voltage of the 1/211 delay line 11 is high.If the bias voltage of the 1/2H delay line 11 is lowered by the bias circuit 37, the output of the AGC circuit 12 will change as shown in FIG. 4(a). A waveform like this is obtained. Similarly, if the charging voltage of the capacitor 54 is higher than the charging voltage of the capacitor 52, a signal with a waveform as shown in FIG. 11
This can be improved by increasing the bias voltage. 1/ like this
As a result of the bias voltage control of the 2H delay line +1, the charging voltages of the two capacitors 52 and 54 become equal even in the case of 3) deviation.

On the other hand, each test signal sent to each input terminal of the two switches 31 and 32 is charged to two sampling capacitors 51 and 53 connected to the IC) I side when the white level is 100%. The two signals are multiplied by the difference voltage by the second differential amplifier 33, for example, by 40 dB.
The signal is amplified to a certain degree and is manually input to the LPF35. The LPF 35 removes high-frequency components from the human input signal and supplies the No. 43 signal to the control signal input end of the AGC circuit 12 . The AGC circuit 12 increases or decreases the gain (AC component of the output signal/AC component of the human power signal) in proportion to the increase or decrease in the DC component of the signal from the LPF 35. That is, when the charging voltage of the sampling capacitor 51 is higher than the charging voltage of the sampling capacitor 53, the output voltage of the differential amplifier 33 decreases and the gain of the AGC circuit 12 becomes smaller; The voltage increases and the gain of the AGC circuit 12 increases, thus the two sampling capacitors 5
The charge voltage of 1.53 becomes the same potential.

As described above, with respect to the 172H delayed signal and the through signal, there is no level difference not only at the upper end and the lower end but also at the intermediate level. As a result, flicker can be effectively suppressed for signals of all levels including intermediate levels.

In the above embodiment, only the video signal part is switched to the test signal, or this test signal becomes the output signal to the reproducing means, so when the synchronization signal is switched to the test signal, it is reproduced with the switched synchronization signal. This is because if there is a phase shift between the synchronization signal and the synchronization signal, there is a risk that the synchronization signal will be disturbed on the reproducing means as jitter. However, by using a PLL circuit or the like and using a clock synchronized with the reproduction synchronization signal, the phase is shifted and the influence of jitter on the reproduction means can be almost suppressed, so the test signal including the synchronization signal can be replaced. I can do it.

Further, the present invention can be configured as shown in FIG. That is, two clamp circuits 1 are provided in the differential amplifier 71.
3. The signal from 14 is directly input, and the output signal of the same amplifier 71 is supplied to the input terminal of the changeover switch 720. Then, the first switching signal (FIG. 3) from the pulse generation circuit 30 causes the switch 72 to be set to the ICH side (to the GG circuit 12 side) and the 2C side to the GG circuit 12 side.
1l side (bias circuit 37 side) and open.

Even with this configuration, when the test signal is at the white 50% level, the switch 72 is connected to the 2C)I side to eliminate the level difference between the 172H delayed signal and the through signal.
The bias voltage of the 2H delay line 11 can be controlled,
Similarly, when the white level is 100%, the switch 72 can be connected to the ICH side to control the gain of the AGC circuit 12 so as to eliminate the level difference between the 1/2H delay signal and the through signal.

[Effects of the Invention] As explained above, according to the present invention, flicker can be effectively suppressed in image information signals of all levels.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing the relationship between synchronization signals and switching signals regarding the embodiment, FIG. 3 is a time chart of main signals of the embodiment, and FIG. The figure shows an example of input/output waveforms of an AGC circuit, Figure 5 shows an example of characteristics of a 1/2H delay line, Figure 6 is a block diagram of another embodiment of the present invention, and Figure 7 is a conventional example. FIG. 2 is an example block diagram. 11... 1/2H delay line, 41... Test signal generator.

Claims (1)

[Scope of Claims] Test signal generation means for generating a test signal; detection means for detecting a level difference between a 1/2 horizontal scanning period delayed signal and a through signal for the test signal from the generation means; and said detection means. A skew compensation circuit comprising: means for changing the bias level of the 1/2 horizontal scanning period delayed signal based on the detection result of the means.