JPS63300626A - Pulse signal isolating circuit - Google Patents

Pulse signal isolating circuit

Info

Publication number
JPS63300626A
JPS63300626A JP13350087A JP13350087A JPS63300626A JP S63300626 A JPS63300626 A JP S63300626A JP 13350087 A JP13350087 A JP 13350087A JP 13350087 A JP13350087 A JP 13350087A JP S63300626 A JPS63300626 A JP S63300626A
Authority
JP
Japan
Prior art keywords
pulse signal
pulse
signal
train
signal train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13350087A
Other languages
Japanese (ja)
Inventor
Chiharu Osawa
大澤 千春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP13350087A priority Critical patent/JPS63300626A/en
Publication of JPS63300626A publication Critical patent/JPS63300626A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To isolate a wide pulse signal even with a pulse transformer having not so much large voltage time project by converting an input pulse signal into a pulse signal of a prescribed length or below, and using a decoding circuit at the output side to decode the signal. CONSTITUTION:An original pulse signal string S1 is supplied to an exclusive OR gate 9 together with a coding clock signal C1, and converted into a coded pulse signal train S2. The signal train S2 and the clock C1 drive the input terminal of a pulse transformer 6 via drivers 10, 11. A coded pulse signal train S2' and a coded clock signal C1' retarded by a propagation delay time are outputted from receivers 12,13. Then, the signal is supplied to an exclusive OR gate 14 and converted into a reproduction pulse signal train S3. The pulse signal train S2 is a pulse signal having equal to or twice the width of the clock signal C1, and in selecting properly the clock signal C1, the isolation of the pulse signal train including the wide pulse is attained by using a transformer whose voltage time product is small.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、互いに異なる電流供給源に属する2つの電
子回路の一方から他方へ伝達されるパルス信号列をパル
ストランスによシ絶縁するための絶縁回路に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for insulating, by a pulse transformer, a pulse signal train transmitted from one of two electronic circuits belonging to different current supply sources to the other. Regarding insulation circuits.

〔従来の技術〕[Conventional technology]

大地電位が異なるような長距離データ伝送や、同一プリ
ント板内であってもノイズ対策や信号レベル変換のため
に2つの電子回路に異なる系統から電源を供給する場合
があυ、このよう外場台は信号の絶縁が不可欠となる。
In some cases, power is supplied to two electronic circuits from different systems for long-distance data transmission where the ground potentials are different, or for noise suppression or signal level conversion even within the same printed board. Signal insulation is essential for the stand.

第6図に信号絶縁回路の従来例を示す。これは、フォト
カプラ3を利用するもので、1はフォトカプラを駆動す
るためのドライバ、2は電流制限抵抗、4はフォトカプ
ラからの信号が入力されるレシーバ、5はレシーバ4の
ためのプルアップ抵抗である。しかし、7オトカプラに
よるものでは、直流に至るまでの幅の広いパルスの伝達
が可能である反面、高速のものは高価かつ占有面積大で
おシ、また経年変化の点で信頼性が低いという欠点があ
った。
FIG. 6 shows a conventional example of a signal isolation circuit. This uses a photocoupler 3, where 1 is a driver for driving the photocoupler, 2 is a current limiting resistor, 4 is a receiver into which the signal from the photocoupler is input, and 5 is a puller for receiver 4. It is up resistance. However, while the 7-point coupler is capable of transmitting wide pulses up to direct current, the high-speed version is expensive, occupies a large area, and has low reliability due to aging. was there.

第7図は、パルストランスによるもので、6がパルスト
ランスである。パルストランスによるものは波形伝達性
、信頼性が高く、高速動作が可能でibb安価である。
In FIG. 7, a pulse transformer is used, and 6 is the pulse transformer. Those using pulse transformers have high waveform transmission properties, high reliability, high-speed operation, and are inexpensive.

なお、同図の他の符号は第6図と同様である。Note that other symbols in the figure are the same as in FIG. 6.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、第8図に示すような、Olたは1が連続する幅
の広いパルスを含むようなパルス信号列を伝送する場合
、電圧時間(ET)積が十分に大きなパルストランスが
必要になる。とζろで、一般にET積の大きなパルスト
ランスは応答速度が遅く、i九人型かつ高価になるとい
う問題がある。
However, when transmitting a pulse signal train including wide pulses in which O1 or 1 are continuous as shown in FIG. 8, a pulse transformer with a sufficiently large voltage-time (ET) product is required. Generally speaking, a pulse transformer with a large ET product has a slow response speed, is small in size, and is expensive.

したがって、この発明は幅の広いパルス信号をそれ程大
きなET積をもたないパルストランスにても絶縁し得る
ようにすることを目的とする。
Therefore, it is an object of the present invention to make it possible to isolate a wide pulse signal even with a pulse transformer that does not have a very large ET product.

〔問題点を解決するための手段〕[Means for solving problems]

互いに異なる電源供給源に属する2、つの電子回路のう
ち、送信側電子回路には一連のパルス信号からなる入力
パルス信号列のもパルス信号を所定軸以上のパルス信号
にそれぞれ変換するための符号化回路を設け、受信側電
子回路にはこの符号化もれたパルス信号列をもとのパル
ス信号列に変換するための復号化回路を設ける。
Of the two electronic circuits that belong to different power supply sources, the transmitter electronic circuit has an input pulse signal train consisting of a series of pulse signals. The receiver electronic circuit is provided with a decoding circuit for converting this encoded pulse signal train into the original pulse signal train.

〔作用〕[Effect]

パルス信号列の送信側には符号化回路を設けて、一連の
パルス信号からなる入力パルス信号列の各パルス信号を
一定長(軸)以下のパルス信号に変換し、受信側には復
号化回路を設けて、符号化されたパルス信号列をもとの
パルス信号列に変換することによシ、両回路間をET積
の小さいパルストランスを用いて絶縁し得るようにする
An encoding circuit is provided on the transmitting side of the pulse signal train to convert each pulse signal of the input pulse signal train consisting of a series of pulse signals into a pulse signal of a certain length (axis) or less, and a decoding circuit is installed on the receiving side. is provided to convert the encoded pulse signal train into the original pulse signal train, thereby making it possible to isolate both circuits using a pulse transformer with a small ET product.

〔実施例〕〔Example〕

第1図はこの発明の特徴金量も良く表わす主要図で、6
a、6bはパルストランス、7は符号化回路である。
Figure 1 is a main diagram that clearly shows the characteristic amount of gold of this invention.
a and 6b are pulse transformers, and 7 is an encoding circuit.

とのような構成において、幅の広いパルス信号を含む原
パルス信号列S1、および符号化用クキツク信号C1が
符号化回路7に入力され、符号化パルス信号列S2が出
力される。符号化パルス信号列S2および符号化用パル
ス信号C1は、パルストランス6a、6bによりおのお
の絶縁されて受信側回路に送られ、復号化回路8を経由
して原パルス信号列S1と相似の再生パルス信号列S3
に変換される。
In this configuration, the original pulse signal train S1 including a wide pulse signal and the encoding crunch signal C1 are input to the encoding circuit 7, and the encoded pulse signal train S2 is output. The encoded pulse signal train S2 and the encoding pulse signal C1 are each insulated by pulse transformers 6a and 6b and sent to the receiving side circuit, and then passed through the decoding circuit 8 to reproduce reproduction pulses similar to the original pulse signal train S1. Signal train S3
is converted to

第2図はこの発明の実施例を示す回路図、第3図はその
動作を説明するための各部波形図である。
FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram of each part for explaining its operation.

これは、第1図を具体化し九もので、排他的論理和(B
OR)ゲート9および差動型ドライバ10.11にて符
号化回路が、また差動型レシーバ12.15およびEO
Rゲート14にて復号化回路が形成されている。符号6
はパルストランスである。
This is a nine-part embodiment of Figure 1, and is an exclusive disjunction (B
OR) Gate 9 and differential driver 10.11 encode the circuit, and differential receiver 12.15 and EO
A decoding circuit is formed by the R gate 14. code 6
is a pulse transformer.

ζ〜で、第5図(イ)に示される原パルス信号列S1が
、同図(ロ)に示される符号化用り四ツク信号C1とと
もにEORゲート9に入力されると、原パルス信号列5
1ti同図(ハ)の如惠符号化パルス信号列$2に変換
される。この符号化パルス信号列S2と符号化用クロッ
ク信号c1と杜、それぞれ差動型ドライバ10.11を
介してパルストランス60入力端を駆動する。パルスト
ランス6の出力端は差動型レシーバ12.13に結合さ
れ、両レシーバからは伝播遅延時間Tdだけ遅れた、同
図(ニ)の如き符号化パルス信号列82’と、同図(ホ
)の如き符号化用クロック信号CI’とが出力される。
At ζ~, when the original pulse signal train S1 shown in FIG. 5
1ti is converted into the coded pulse signal train $2 shown in FIG. The encoded pulse signal train S2, the encoding clock signal c1, and the encoder drive the input end of the pulse transformer 60 through differential drivers 10 and 11, respectively. The output end of the pulse transformer 6 is coupled to a differential receiver 12.13, and from both receivers, an encoded pulse signal train 82' as shown in FIG. ) is output as an encoding clock signal CI'.

符号化パルス信号列82’と符号化用クロック信号CI
’とは別のEORゲート14に入力され、同図(へ)の
如き再生パルス信号列S3に変換される。
Encoded pulse signal train 82' and encoding clock signal CI
' is input to an EOR gate 14 different from ', and converted into a reproduction pulse signal sequence S3 as shown in FIG.

なお、EORゲート9から出力される符号化パルス信号
列S2は、マンチェスタ符号またはパイフェーズ符号と
呼ばれ、符号化用クロック信号C1と同じか2倍の長さ
く幅)のパルス信号となることが知られている。従って
、符号化用クロック信号C1を適当に選択することによ
シ、ET積の小さい安価なパルストランスを用いて、幅
の広いパルスを含むパルス信号列の絶縁が可能になる。
The encoded pulse signal train S2 output from the EOR gate 9 is called a Manchester code or a pi-phase code, and can be a pulse signal with the same length or width as the encoding clock signal C1. Are known. Therefore, by appropriately selecting the encoding clock signal C1, it is possible to isolate a pulse signal train including wide pulses using an inexpensive pulse transformer with a small ET product.

第4図拡開の符号化方式を示すもので、これはf/2f
符号またはPDM(パルス期間変調)符号と呼ばれる。
Figure 4 shows the encoding method for expansion, which is f/2f
code or PDM (Pulse Period Modulation) code.

この場合も、原パルス信号列の各パルス信号はそれぞれ
単位パルス幅Tu以下のパルス信号に変換されるので、
上記と同様の効果が得られる。
In this case, each pulse signal of the original pulse signal train is converted into a pulse signal with a unit pulse width Tu or less, so
The same effect as above can be obtained.

第5図はこの発明の別の実施例を示す概要図である。こ
れは、復号化回路8aにクロック抽出機能を持たせるこ
とにより、上記で使用している各種符号を初め、クロッ
ク成分を含ませるような符号化を行なう場合でも、符号
化用クロック信号C1のための信号線およびパルストラ
ンス6b’を省略し得るようにしたもので、特に長距離
データ伝送などに適している。また、パルストランスに
接続されるドライバ、レシーバは必ずしも第2図のよう
な差動壓である必要はなく、第7図のような形式のもの
でもよい。
FIG. 5 is a schematic diagram showing another embodiment of the present invention. By providing the decoding circuit 8a with a clock extraction function, even when encoding that includes a clock component, including the various codes used above, the clock signal C1 for encoding can be used. The signal line and pulse transformer 6b' can be omitted, making it particularly suitable for long-distance data transmission. Further, the driver and receiver connected to the pulse transformer do not necessarily have to be differential circuits as shown in FIG. 2, but may be of the type shown in FIG. 7.

〔発明の効果〕〔Effect of the invention〕

この発明によれば、パルストランスの入力側には符号化
回路を設けて、入力される各パルス信号を一定長(一定
@)以下のパルス信号に変換し、これを出力側の復号化
回路にて復号化するようにしたので、ET積の小さいパ
ルストランスを用いて、幅の広いパルスを含むパルス信
号列の絶縁が可能になる利点がもたらされる。
According to this invention, an encoding circuit is provided on the input side of the pulse transformer to convert each input pulse signal into a pulse signal of a certain length (constant @) or less, and this is sent to the decoding circuit on the output side. Since the decoding is performed using a pulse transformer having a small ET product, it is possible to isolate a pulse signal train including wide pulses using a pulse transformer having a small ET product.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の特徴を最も良く表わす主要図、第2
図は仁の発明の実施例を示す回路図、第6図はその動作
を説明するための各部波形図、第4図は符号化方式の別
の例を説明するための波形図、第5図はこの発明の他の
実施例含水す概要図、第6図はパルス信号絶縁回路の従
来例を示す回路図、第7図はパルス信号絶縁回路の他の
従来例を示す回路図、第8図はotたは1が連続する幅
の広いパルスを含むパルス信号列の一例を示す波形図で
ある。 符号説明 1・・・・・・ドライバ、2・・・・・・電流制限抵抗
、3・・・・・・フォトカプラ、4・・・・・・レシー
バ、5・・・・・・プルアップ抵抗、6.6a、6b・
・・・・・パルストランス、7・・・・・・符号化回路
、8,8a・・・・・・復号化回路、9゜14・・・・
・・排他的論理和(BOR)ゲート、10゜11・・・
・・・差動型ドライバ、12.13・・・・・・差動型
レシーバ、Sl・・・・・・原パルス信号、82・・・
・・・符号化パルス信号列、S3・・・・・・再生パル
ス信号列、C1・・・・・・符号化用クロック信号列。 第 1 グ ([ (I 第 2 図 (二 第 3 図 1)C1 −)S2 −> S; 第4図 雷 5 図 第6図 2□lけ亡・ 1X+ルストラレ又 蘂8図
Figure 1 is the main diagram that best represents the features of this invention;
Figure 6 is a circuit diagram showing an embodiment of Jin's invention, Figure 6 is a waveform diagram of each part to explain its operation, Figure 4 is a waveform diagram to explain another example of the encoding method, and Figure 5. 6 is a circuit diagram showing a conventional example of a pulse signal insulating circuit, FIG. 7 is a circuit diagram showing another conventional example of a pulse signal insulating circuit, and FIG. FIG. 2 is a waveform diagram showing an example of a pulse signal train including wide pulses in which ot or 1 are successive. Symbol explanation 1...Driver, 2...Current limiting resistor, 3...Photocoupler, 4...Receiver, 5...Pull-up Resistance, 6.6a, 6b・
...Pulse transformer, 7...Encoding circuit, 8,8a...Decoding circuit, 9゜14...
・・Exclusive OR (BOR) gate, 10°11...
...Differential driver, 12.13...Differential receiver, Sl...Original pulse signal, 82...
. . . Encoded pulse signal train, S3 . . . Reproduction pulse signal train, C1 . . . Encoding clock signal train. 1st gu ([ (I 2nd 3rd 1) C1 -) S2 ->S; 4th thunder 5 fig.

Claims (1)

【特許請求の範囲】 互いに異なる電源供給源に属する2つの電子回路の一方
から他方へ伝達されるパルス信号列をパルストランスに
より絶縁すべく、 送信側電子回路には一連のパルス信号からなる入力パル
ス信号列の各パルス信号を所定幅以下のパルス信号にそ
れぞれ変換するための符号化回路を設け、 受信側電子回路には前記符号化されたパルス信号列をも
とのパルス信号列に変換するための復号化回路を設けて
なることを特徴とするパルス信号絶縁回路。
[Claims] In order to isolate a pulse signal train transmitted from one of two electronic circuits belonging to different power supply sources to the other by a pulse transformer, an input pulse consisting of a series of pulse signals is provided to the transmitting electronic circuit. An encoding circuit is provided for converting each pulse signal of the signal train into a pulse signal having a predetermined width or less, and the receiving electronic circuit is provided with an encoding circuit for converting the encoded pulse signal train into the original pulse signal train. 1. A pulse signal isolation circuit comprising a decoding circuit.
JP13350087A 1987-05-30 1987-05-30 Pulse signal isolating circuit Pending JPS63300626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13350087A JPS63300626A (en) 1987-05-30 1987-05-30 Pulse signal isolating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13350087A JPS63300626A (en) 1987-05-30 1987-05-30 Pulse signal isolating circuit

Publications (1)

Publication Number Publication Date
JPS63300626A true JPS63300626A (en) 1988-12-07

Family

ID=15106223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13350087A Pending JPS63300626A (en) 1987-05-30 1987-05-30 Pulse signal isolating circuit

Country Status (1)

Country Link
JP (1) JPS63300626A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116764A (en) * 2012-12-10 2014-06-26 Onkyo Corp Audio signal transmission device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014116764A (en) * 2012-12-10 2014-06-26 Onkyo Corp Audio signal transmission device

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