KR940010562A - Duobinary conversion circuit - Google Patents

Duobinary conversion circuit Download PDF

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Publication number
KR940010562A
KR940010562A KR1019920020083A KR920020083A KR940010562A KR 940010562 A KR940010562 A KR 940010562A KR 1019920020083 A KR1019920020083 A KR 1019920020083A KR 920020083 A KR920020083 A KR 920020083A KR 940010562 A KR940010562 A KR 940010562A
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KR
South Korea
Prior art keywords
output
input terminal
binary data
flip
gate
Prior art date
Application number
KR1019920020083A
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Korean (ko)
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KR950007978B1 (en
Inventor
이태호
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배순훈
대우전자 주식회사
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Priority to KR1019920020083A priority Critical patent/KR950007978B1/en
Publication of KR940010562A publication Critical patent/KR940010562A/en
Application granted granted Critical
Publication of KR950007978B1 publication Critical patent/KR950007978B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

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  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

본 발명은 유럽형 D/D2MAC 전송 방식에 사용되는 듀오바이너리(Duobinary) 데이타를 얻기 위한 듀오바이너리 변환 회로에 관한 것으로서, 바이너리 데이타의 입력단에 클럭단이 연결되고 데이타 입력단에는 부출력단(Q)이 연결된 플립플롭 수단(21)과, 상기 플립플롭 수단(21)의 출력단(Q)과 바이너리 데이타 입력단에 입력단이 연결된 앤드게이트(22)와, 상기 플립플롭 수단(21)의 부출력단(Q)과 바이너리 데이타 입력단에 입력단이 연결된 낸드게이트(23)과, 상기 앤드게이트(22)와 낸드게이트(23)의 출력단에 연결되어 듀오바이너리 데이타를 출력하는 출력수단(3)각 구비한 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a duobinary conversion circuit for obtaining duobinary data used in the European D / D 2 MAC transmission scheme, wherein a clock stage is connected to an input terminal of binary data and a sub-output terminal (Q) is connected to the data input terminal. Connected flip-flop means 21, an output terminal Q of the flip-flop means 21, an AND gate 22 connected to an input terminal of a binary data input terminal, a sub-output end Q of the flip-flop means 21, NAND gate 23 connected to the input terminal of the binary data input terminal, and output means (3) connected to the output terminal of the AND gate 22 and the NAND gate 23 to output the duo binary data.

Description

듀오바이너리 변환 회로Duobinary conversion circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 유럽전송 방식의 베이스 밴드 비디오 파형도,1 is a baseband video waveform diagram of the European transmission method,

제2도는 바이너리와 듀오바이너리 코딩방식에 대한 비교 파형도,2 is a comparison waveform diagram of binary and duo binary coding schemes,

제4도는 본 발명에 따른 듀오바이너리 파형도,4 is a diagram of a duobinary waveform according to the present invention,

제5도는 본 발명에 따른 프리코딩 데이타 파형도.5 is a precoding data waveform diagram according to the present invention.

Claims (3)

바이너리 데이타를 듀오바이너리 데이타로 변환하는 회로에 있어서, 바이너리 데이타의 입력단에 클럭단이 연결되고 데이타 입력단에는 부출력단(Q)이 연결된 플립플롭 수단(21)과, 상기 플립필롭 수단(21)의 출력단(Q)과 바이너리 데이타 입력단에 입력단이 연결된 앤드게이트(22)와, 상기 플립플롭 수단(21)의 부출력단(Q)과 바이너리 데이타 입력단에 입력단이 연결된 앤드게이트(22)와, 상기 앤드게이트(22)와 낸드게이트(23)의 출력단에 연결되어 듀오바이너리 데이타를 출력하는 출력수단(3)을 구비한 것을 특징으로 하는 듀오바이너리 변환 회로.In a circuit for converting binary data into duo binary data, a flip-flop means 21 having a clock terminal connected to an input terminal of binary data and a sub-output terminal Q connected to a data input terminal, and an output terminal of the flip-flop means 21. An AND gate 22 having an input terminal connected to Q and a binary data input terminal, an AND gate 22 having an input terminal connected to a sub output terminal Q of the flip-flop means 21 and a binary data input terminal, and an AND gate ( 22) and an output means (3) connected to an output terminal of the NAND gate (23) to output duo binary data. 제1항에 있어서, 상기 플립플롭 수단(21)은 D플립플롭 소자로 구성되는 것을 특징으로 하는 듀오바이너리 변환 회로.The duobinary conversion circuit according to claim 1, characterized in that said flip-flop means (21) consists of a D flip-flop element. 제1항에 있어서, 상기 출력 수단(3)은, 상기 앤드게이트(22)와 낸드게이트(23)의 출력단에 각각 연결된 제1 및 제2저항(R)과, 상기 제1 및 제2저항(R)과 출력단 사이에 연결된 콘덴서(C)와, 상기 제1 및 제2저항(R)과 접지 사이에 연결된 제3저항(R)으로 구성되는 것을 특징으로 하는 듀오바이너리 변환 회로.The output device (3) of claim 1, wherein the output means (3) comprises first and second resistors (R) connected to the output terminals of the AND gate (22) and the NAND gate (23), and the first and second resistors ( And a third resistor (R) connected between the first and second resistors (R) and ground, and a capacitor (C) connected between R) and an output terminal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019920020083A 1992-10-29 1992-10-29 Duo binary conversion circuit KR950007978B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920020083A KR950007978B1 (en) 1992-10-29 1992-10-29 Duo binary conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920020083A KR950007978B1 (en) 1992-10-29 1992-10-29 Duo binary conversion circuit

Publications (2)

Publication Number Publication Date
KR940010562A true KR940010562A (en) 1994-05-26
KR950007978B1 KR950007978B1 (en) 1995-07-21

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ID=19342041

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920020083A KR950007978B1 (en) 1992-10-29 1992-10-29 Duo binary conversion circuit

Country Status (1)

Country Link
KR (1) KR950007978B1 (en)

Also Published As

Publication number Publication date
KR950007978B1 (en) 1995-07-21

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