JPS63300529A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63300529A JPS63300529A JP62137235A JP13723587A JPS63300529A JP S63300529 A JPS63300529 A JP S63300529A JP 62137235 A JP62137235 A JP 62137235A JP 13723587 A JP13723587 A JP 13723587A JP S63300529 A JPS63300529 A JP S63300529A
- Authority
- JP
- Japan
- Prior art keywords
- write
- fuse
- write enable
- circuit
- disable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 13
- 230000005540 biological transmission Effects 0.000 claims abstract description 9
- 230000002401 inhibitory effect Effects 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 230000004044 response Effects 0.000 claims description 3
- 230000008054 signal transmission Effects 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 7
- 230000005611 electricity Effects 0.000 abstract description 6
- 230000003068 static effect Effects 0.000 abstract description 6
- 238000009826 distribution Methods 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 238000005520 cutting process Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路に関し、特にＲＯＭ部への書込
みが完了した後に再書込みを禁止するための多結晶シリ
コンの書込み禁止用ヒユーズを有するＭＯＳ型の半導体
集積回路に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit, and in particular to a MOS having a polycrystalline silicon write-inhibiting fuse for inhibiting rewriting after writing to a ROM section is completed. This invention relates to type semiconductor integrated circuits.
従来、この種の半導体集積回路は、第２図に示すように
、書込み信号Ｓｗにより所定のメモリセルにデータを書
込むＥＰＲＯＭ部５と、一端が外部端子の書込み可否設
定端子Ｔ、に接続され、ＥＰＲＯＭ部５への書込みが完
了した後に再書込みを禁止するための多結晶シリコンの
書込み禁止用ヒユーズ２と、トランジスタＱｓ、Ｑ４及
びインバータ３１を含んで構成され、入力端が書込み禁
止用ヒユーズ２の他端に接続され、書込み可否設定端子
Ｔ１に所定の電位を与えることにより書込み可否信号を
出力する書込み可否設定回路３と、書込み可否信号によ
り書込み信号Ｓｗの伝達を制御するＮＡＮＤ型のゲート
回路４とを有する構成となっていた。Conventionally, as shown in FIG. 2, this type of semiconductor integrated circuit has an EPROM section 5 that writes data into a predetermined memory cell in response to a write signal Sw, and one end connected to a write enable/disable setting terminal T, which is an external terminal. , a polycrystalline silicon write-inhibiting fuse 2 for inhibiting rewriting after writing to the EPROM section 5 is completed, transistors Qs, Q4, and an inverter 31, and the input terminal is the write-inhibiting fuse 2. A write enable/disable setting circuit 3 is connected to the other end and outputs a write enable/disable signal by applying a predetermined potential to a write enable/disable setting terminal T1, and a NAND gate circuit controls transmission of the write signal Sw based on the write enable/disable signal. 4.
第３図は第２図の主要部分の等価回路図である。FIG. 3 is an equivalent circuit diagram of the main parts of FIG. 2.
第２図に示されたトランジスタＱ３は抵抗素子として動
作し、トランジスタＱ４はダイオードとして動作する。Transistor Q3 shown in FIG. 2 operates as a resistive element, and transistor Q4 operates as a diode.
ここで、書込み可否設定端子Ｔ１が開放状態であると、
トランジスタＱ３によりインバータ３１の入力端はプル
アップされてＮＡＮＤ型のゲート回路４の入力端の書込
み可否信号は低レベルとなり、書込み信号Ｓｗの伝達を
禁止する。Here, if the write enable/disable setting terminal T1 is in an open state,
The input terminal of the inverter 31 is pulled up by the transistor Q3, and the write enable/disable signal at the input terminal of the NAND type gate circuit 4 becomes low level, thereby prohibiting transmission of the write signal Sw.
次に、書込み可否設定端子Ｔ１と接地間に所定の値の抵
抗を接続してインバータ３１の入力端のレベルがインバ
ータ３１のしきい値を越えるように書込み可否信号を高
レベルにすると、出力は反転して書込み信号Ｓｗはゲー
ト回路４により伝達される。Next, a resistor of a predetermined value is connected between the write enable/disable setting terminal T1 and the ground, and the write enable/disable signal is set to a high level so that the level at the input terminal of the inverter 31 exceeds the threshold value of the inverter 31. The inverted write signal Sw is transmitted by the gate circuit 4.
ＥＰＲＯＭ部５の書込みが完了すると、その後の再書込
みを禁止するために、書込み禁止用ヒユーズ２を切断す
る。この切断方法は、書込み可否設定端子Ｔ１にトラン
ジスタＱ４がブレークダウンする電圧を印加し、その電
流により切断する。When the writing to the EPROM section 5 is completed, the write inhibiting fuse 2 is cut off in order to prohibit subsequent rewriting. In this cutting method, a voltage that causes breakdown of the transistor Q4 is applied to the write enable/disable setting terminal T1, and the current is used to cut the transistor.
書込み禁止用ヒユーズ２は、第４図に示すように、中心
部の寸法が０．５〜１．５μｍ程度の非常に細い構造と
なっている。As shown in FIG. 4, the write-inhibiting fuse 2 has a very thin structure with a central dimension of about 0.5 to 1.5 μm.
上述した従来の半導体集積回路は、書込み禁止用ヒユー
ズ２の一端が外部端子である書込み可否設定端子Ｔ１に
接続され、かつ中心部は非常に細い構造となっているの
で、拡散後の製造工程、流通工程において、静電気によ
り書込み禁止用ヒユーズ２が書込み前に破壊してしまう
という欠点がある。In the conventional semiconductor integrated circuit described above, one end of the write inhibit fuse 2 is connected to the write enable/disable setting terminal T1, which is an external terminal, and the center part has a very thin structure. In the distribution process, there is a drawback that the write-inhibiting fuse 2 is destroyed before writing due to static electricity.
また、書込み前に書込み禁止用ヒユーズ２が破壊するの
を防止するためには、拡散直後に書込みを行い直ちに書
込み禁止用ヒユーズ２を切断しなげればならないので、
適用範囲が限定されるという欠点がある。In addition, in order to prevent the write-protection fuse 2 from being destroyed before writing, it is necessary to write immediately after diffusion and immediately disconnect the write-protection fuse 2.
The disadvantage is that the scope of application is limited.
本発明の目的は、拡散後の製造工程、流通工程において
、静電気により書込み禁止用ヒユーズが破壊されるのを
防止し、適用範囲を拡大することができる半導体集積回
路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can prevent a write inhibit fuse from being destroyed by static electricity during the manufacturing process and distribution process after diffusion, and can expand the range of application.
本発明は、書込み信号により所定のメモリセルにデータ
を書込むＲＯＭ部と、一端が書込み可否設定端子に接続
され、前記ＲＯＭ部への書込みが完了した後に再書込み
を禁止するための多結晶シリコンの書込み禁止用ヒユー
ズと、入力端がこの書込み禁止用ヒユーズの他端に接続
され、前記書込み可否設定端子に所定の電位を与えるこ
とにより書込み可否信号を出力する書込み可否設定回路
と、前記書込み可否信号により前記書込み信号の伝達を
制御するゲート回路とを有する半導体集積回路において
、前記書込み可否設定端子と前記書込み禁止用ヒユーズ
との間に、トランスミッションゲート型の保護回路を設
けて構成される。The present invention includes a ROM section that writes data into a predetermined memory cell in response to a write signal, and a polycrystalline silicon ROM section that has one end connected to a write enable/disable setting terminal and that prohibits rewriting after writing to the ROM section is completed. a write enable/disable fuse, a write enable/disable setting circuit whose input end is connected to the other end of the write enable/disable fuse and which outputs a write enable/disable signal by applying a predetermined potential to the write enable/disable setting terminal; In a semiconductor integrated circuit having a gate circuit that controls transmission of the write signal by a signal, a transmission gate type protection circuit is provided between the write enable/disable setting terminal and the write inhibit fuse.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１［！Ｉは本発明の一実施例を示す回路図である。1st [! I is a circuit diagram showing one embodiment of the present invention.
この実施例が第２図に示された従来の半導体集積回路と
相違する点は、書込み可否設定端子Ｔ１と書込み禁止用
ヒユーズ２との間に、トランジスタＱｓ 、 Ｑａ及び
インバータ１１を含んで構成されたトランスミッション
ゲート型の保護回路１を設けた点である。This embodiment is different from the conventional semiconductor integrated circuit shown in FIG. The point is that a transmission gate type protection circuit 1 is provided.
この保護回路１は、製造工程、流通工程においては、ト
ランジスタＱｌ、Ｑ２のソース・ドレイン間が保護ダイ
オードとして働き、書込み禁止用ヒユーズ２が静電気に
より破壊されるのを防止する。In this protection circuit 1, during the manufacturing process and distribution process, the source-drain region of the transistors Ql and Q2 acts as a protection diode to prevent the write inhibit fuse 2 from being destroyed by static electricity.
また、書込み可否を設定するときや書込み禁止用ヒユー
ズ２を切断するときには、保護回路１の制御電極に所定
の電圧Ｖ、を与えて導通状態とすることにより、従来と
同様の方法で行うことができる。Furthermore, when setting whether or not to allow writing or cutting off the write inhibit fuse 2, it can be done in the same manner as in the past by applying a predetermined voltage V to the control electrode of the protection circuit 1 to make it conductive. can.
以上説明したように本発明は、書込み可否設定端子と書
込み禁止用ヒユーズとの間にトランスミッションゲート
型の保護回路を設ける構成とすることにより、保護回路
のトランジスタのソース・ドレイン間が保護ダイオード
として働くので、製造工程、流通工程における静電気に
よる書込み禁止用ヒユーズの破壊を防止することができ
、ＲＯＭの書込み及び書込み禁止用ヒユーズの切断がユ
ーザー側でも可能となるので適用範囲を拡大することが
できる効果がある。As explained above, the present invention has a configuration in which a transmission gate type protection circuit is provided between the write enable/disable setting terminal and the write inhibit fuse, so that the source and drain of the transistor of the protection circuit acts as a protection diode. Therefore, it is possible to prevent write-protection fuses from being destroyed due to static electricity during manufacturing and distribution processes, and the user can also write to the ROM and cut write-protection fuses, so the range of application can be expanded. There is.
第１図は本発明の一実施例を示す回路図、第２図は従来
の半導体集積回路の一例を示す回路図、第３図は第２図
に示された半導体集積回路の主要部分の等価回路図、第
４図は第２図に示された半導体集積回路の書込み禁止用
ヒユーズの部分の平面図である。
１・・・保護回路、２・・・書込み禁止用ヒユーズ、３
・・・書込み可否設定回路、４・・・ゲート回路、５・
・・ＥＰＲＯＭ部、６・・・半導体チップ、７・・・絶
縁膜、８・・・金属配線、９・・・コンタクトホール、
１１．３１・・・インバータ、Ｑ ｌ” Ｑ ａ・・・
トランジスタ、Ｔ。
・・・書込み可否設定端子。
兜 １ 図
嶌２図
第３図
第４図Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a conventional semiconductor integrated circuit, and Fig. 3 is an equivalent of the main parts of the semiconductor integrated circuit shown in Fig. 2. The circuit diagram, FIG. 4, is a plan view of the write inhibit fuse portion of the semiconductor integrated circuit shown in FIG. 2. 1...Protection circuit, 2...Write protection fuse, 3
...Writing permission setting circuit, 4...Gate circuit, 5.
...EPROM section, 6... semiconductor chip, 7... insulating film, 8... metal wiring, 9... contact hole,
11.31... Inverter, Q l" Q a...
Transistor, T. ...Write enable/disable setting terminal. Kabuto 1 Figure 2 Figure 3 Figure 4
Claims (1)
ＲＯＭ部と、一端が書込み可否設定端子に接続され、前
記ＲＯＭ部への書込みが完了した後に再書込みを禁止す
るための多結晶シリコンの書込み禁止用ヒューズと、入
力端がこの書込み禁止用ヒューズの他端に接続され、前
記書込み可否設定端子に所定の電位を与えることにより
書込み可否信号を出力する書込み可否設定回路と、前記
書込み可否信号により前記書込み信号の伝達を制御する
ゲート回路とを有する半導体集積回路において、前記書
込み可否設定端子と前記書込み禁止用ヒューズとの間に
、トランスミッションゲート型の保護回路を設けたこと
を特徴とする半導体集積回路。A ROM section that writes data to a predetermined memory cell in response to a write signal, and a polycrystalline silicon write-inhibiting section whose one end is connected to a write enable/disable setting terminal to prohibit rewriting after writing to the ROM section is completed. a fuse, a write enable/disable setting circuit whose input end is connected to the other end of the write inhibit fuse and which outputs a write enable/disable signal by applying a predetermined potential to the write enable/disable setting terminal; 1. A semiconductor integrated circuit having a gate circuit for controlling signal transmission, characterized in that a transmission gate type protection circuit is provided between the write enable/disable setting terminal and the write inhibit fuse.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62137235A JPS63300529A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62137235A JPS63300529A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63300529A true JPS63300529A (en) | 1988-12-07 |
Family
ID=15193937
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62137235A Pending JPS63300529A (en) | 1987-05-29 | 1987-05-29 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63300529A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0440331A2 (en) * | 1990-01-29 | 1991-08-07 | International Business Machines Corporation | Integrated circuit with pass gate multiplexer receiver circuit |
| JP2006073553A (en) * | 2004-08-31 | 2006-03-16 | Nec Electronics Corp | Fuse trimming circuit |
| JP2007103903A (en) * | 2005-10-06 | 2007-04-19 | Renei Kagi Kofun Yugenkoshi | Esd (electrostatic discharge) protection equipment for programmable device |
-
1987
- 1987-05-29 JP JP62137235A patent/JPS63300529A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0440331A2 (en) * | 1990-01-29 | 1991-08-07 | International Business Machines Corporation | Integrated circuit with pass gate multiplexer receiver circuit |
| EP0440331A3 (en) * | 1990-01-29 | 1994-02-02 | Ibm | |
| JP2006073553A (en) * | 2004-08-31 | 2006-03-16 | Nec Electronics Corp | Fuse trimming circuit |
| JP2007103903A (en) * | 2005-10-06 | 2007-04-19 | Renei Kagi Kofun Yugenkoshi | Esd (electrostatic discharge) protection equipment for programmable device |
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