JPS63299157A - Capacitor element - Google Patents

Abstract

PURPOSE:To increase a capacity without increasing an area by forming a meshlike uneven surface on a semiconductor substrate to increase the capacity per unit area. CONSTITUTION:After a first oxide film 2 is formed on a semiconductor substrate 1, the first oxide film is partly removed by a photoetching method along thick lateral and longitudinal mesh lines to form a meshlike pattern having oxide film remainders M aligned laterally and longitudinally at an interval of lateral direction W and longitudinal direction H. Then, with the remaining oxide film M as an etching resistant mask it is removed by etching in a depth, such as approx. 1mum by a normal RIE method. Thereafter, the other film 2 is removed by a normal photoetching method except part of the film 2 at the periphery. Subsequently, a high concentration impurity diffused layer 3 having the same conductivity type as that of the substrate 1 is formed by a thermal diffusing method. Then, a second oxide film 4 having approx. 500Angstrom thick, a nitride film 5 having approx. 1000Angstrom and an electrode leading window are formed similarly to a conventional method. Eventually, aluminum is deposited approx. 1.5mum thick to form both end electrodes 6, 7 of a capacity element.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention particularly relates to large capacity circuit elements among several types of circuit elements forming an integrated circuit.

[Conventional technology]

A general manufacturing method for obtaining large capacitance elements in integrated circuits is shown in the plan view of FIG. 4 and in FIGS. 5(a) to (C).
This will be explained with reference to a cross-sectional view. First, after thermally oxidizing the semiconductor substrate 1 to form the first oxide film 22 as in the fifth session),
A part of the first oxide film 22 is etched by ordinary photolithography,
The chipping is removed to expose a part of the semiconductor substrate 1. Then, an impurity diffusion layer 23 exhibiting the same conductivity type as the semiconductor substrate 1 (for example, a surface concentration of 5×10 20 /
i, depth 1 μm). Next, as shown in FIG. 5(b), a second oxide film 4 of about s o o

Next, after forming a nitride film 5 of about 1000× by a normal vapor growth method, a nitride film 5 of about 1000× is formed by a normal photolithography method).
A part of the oxide film 4 is etched and removed, and a window for drawing out the characteristics is opened. Next, as shown in FIG. 5(c), At is deposited to a thickness L5 μm to form electrodes 6 and 7 at both ends of the capacitive element.

[Problem that the invention seeks to solve]

In a typical analog integrated circuit, a large-capacitance element of about 1 to zopF' is required as a DC cut or feedback capacitor, but when conventional manufacturing methods are used, for example,
An area of approximately 34,000 μ2 is required to form a pF' capacitive element. However, such large-area devices are limited to integrated circuit chips.

This is undesirable from the viewpoint of high integration. Therefore, to improve this point, it is necessary to increase the capacitance per unit area by making the insulating film that constitutes the capacitive element thinner or by using an insulating film with a higher dielectric constant. being tested. However, making the insulating film thinner has the drawbacks of worsening the absolute precision of the capacitance (increasing the variation) and lowering the breakdown voltage between the capacitor electrodes.On the other hand, the insulating film has a high dielectric constant. This is because a nitride film (7 out of 3) has not yet been put to practical use. ◎ [Means for solving the problem] In order to solve the above problem, in the present invention, a mesh-like uneven structure is formed on the semiconductor substrate. By doing so, the capacity per unit area is increased, and a large capacity is achieved without increasing the area.

〔Example〕

Next, the present invention will be explained using examples.

FIG. 1 is a plan view of an embodiment of the present invention, and FIG. 2 (a) to (
d) is a cross-sectional view of the material section corresponding to the section line AA in FIG. 1 for explaining a method of manufacturing a large-capacity element according to an embodiment of the present invention. First, as shown in FIG. 2(a), after forming a first oxide film 2 on a semiconductor substrate 1, the first oxide film is partially etched along thick vertical and horizontal mesh lines by photolithography. Then, as shown in FIG. 1, a shell-shaped pattern is formed having residual oxide film portions M arranged vertically and horizontally at intervals of W in the horizontal direction and H in the vertical direction. Next, using the remaining oxide film M as a corrosion-resistant mask, apply normal R.
The IE method is used to remove the chippings, for example, to a depth of about 1 μm. Next, as shown in FIG. 2(b), the oxide film 2 in the peripheral area is
The remaining oxide film 2 is removed by normal photolithography, leaving a part of the oxide film 2. Next, the semiconductor substrate 1 is removed by a thermal diffusion method.
A highly concentrated impurity diffusion layer (for example, surface concentration 5×10"/cII!i, depth 1 μm) 3 exhibiting the same conductive tone as shown in FIG. 2(c) is formed. Next, as shown in FIG. A second oxide film 4 with a thickness of 500×, a nitride film 5 with a thickness of approximately 1000×, and a window for drawing out the electrodes are formed.
As shown in Figure (d), At is deposited to a thickness of approximately 5 μm to form electrodes 6 and 7 at both ends of the capacitive element.

FIGS. 3(a) to 3(d) are cross-sectional views of a large-capacity element according to another embodiment of the present invention in order to explain a manufacturing method thereof. First, as shown in FIG. 3(a), after thermally oxidizing the semiconductor substrate 1 to form a first oxide film 12 (for example, about L2 μm thick), a part of the oxide film 12 is removed by photolithography. Etching is performed to form a convex and concave surface with a 2-millimeter pattern (for example, by removing to μm using the RIE method and leaving 0.2 μm). Next, a polysilicon layer 13 (for example, about 0.3 μm thick) is formed by a normal vapor phase growth method, and then a polysilicon layer 13 is formed.
Part 3 is machined and removed. Next, in Figure 3 (b
), high-dose ion implantation on the top surface (for example, P”
. Next, low temperature thermal oxidation (
For example, 900℃, 30 minutes, oxidizing atmosphere), and then
As shown in Figure (C), the second oxide film 14 has a thickness of about 500X.
After forming, a nitride film 15 having a thickness of about 1000× is formed by vapor layer growth. Next, as shown in FIG. 3(d), a part of the nitride film 15 and oxide film 14 is etched and removed by photolithography, a window for taking out the electrode is opened, and finally, A/ is removed. The electrodes 6 and 7 are formed by vapor deposition to a thickness of 5 μm.

〔Effect of the invention〕

As can be seen from the above embodiments, in the capacitive element to which the present invention is applied, for example, the W and H of the mesh pattern mask of the first oxide film shown in FIG.

When K is 2 μm, l, 5 μm, and 2 μm, and the groove depth d is 1 μm, the capacitance per unit area of the capacitive element is:
This is approximately L4 times that of the conventional flat structure. This is because the actual capacitance area increases due to the unevenness of the semiconductor substrate. In order to obtain a greater effect, the mesh pattern pattern of the first oxide film should be made smaller (especially H>W), or the groove depth d should be made deeper. . Further, according to the present invention, the cross-sectional angle of the unevenness of the semiconductor substrate 1 shown in FIG. In this example, approximately 60
70@, so there is no concern about breakage of the At electrode.

[Brief explanation of drawings]

FIG. 1 is a plan view of an embodiment of the present invention, and FIGS. 3 is a cross-sectional view of the process order corresponding to cutting line A, FIG. 3 is a cross-sectional view of the process order for explaining the manufacturing process of a large-capacity element according to another embodiment of the present invention, and FIG. 4 is a cross-sectional view of a conventional large-capacity element. Plan view of Figure 5(a)
1 to c) are cross-sectional views illustrating the manufacturing process of a conventional large-capacity element. 1... Semiconductor substrate, 2, 12... First
Oxide film, 3.23... Impurity diffusion layer, 4,24
...Second oxide film, 5...Nitride film, 6,
7... Electrode. lmi・2I 謬t Figure 1 Z diagram

Claims (1)

[Claims] a diffusion layer containing a large amount of impurities exhibiting one conductivity type and functioning as a first electrode formed on a semiconductor substrate; at least one type of dielectric material formed on the diffusion layer;
1. A capacitive element comprising at least one type of conductive material serving as a second electrode, wherein the semiconductor substrate surface has a mesh-like uneven surface.