JPH06151707A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPH06151707A
JPH06151707A JP30375692A JP30375692A JPH06151707A JP H06151707 A JPH06151707 A JP H06151707A JP 30375692 A JP30375692 A JP 30375692A JP 30375692 A JP30375692 A JP 30375692A JP H06151707 A JPH06151707 A JP H06151707A
Authority
JP
Japan
Prior art keywords
film
capacitor
lower electrode
silicon nitride
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP30375692A
Other languages
Japanese (ja)
Other versions
JP2761334B2 (en
Inventor
Shigeyuki Katayama
茂行 片山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP30375692A priority Critical patent/JP2761334B2/en
Publication of JPH06151707A publication Critical patent/JPH06151707A/en
Application granted granted Critical
Publication of JP2761334B2 publication Critical patent/JP2761334B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To provide a semiconductor device manufacturing method with which a semiconductor device can be manufactured easily by electrically connecting it to other circuit elements completely while a large capacitor is being manufactured without being affected by stray capacity and the like, and the capacitor, to be electrically connected to other IC-constituting elements, is formed on the insulating film which is insulated from a circuit element. CONSTITUTION:A capacitor part is formed by successively laminating a lower electrode film, a silicon nitride film and an upper electrode film on the insulating film provided on the surface of a semiconductor substrate and by conducting a patterning operation thereon. The lower electrode is exposed by providing a contact hole 2a on the electrode terminal forming part of the lower electrode. A recessed part 2b is formed by etching a silicon nitride film 6 which is exposed to the side face of the contact hole 2a, the end parts 2c of the contact hole 2a are smoothed by reflowing by conducting a heat treatment, the oxide film on the lower electrode 3, which is oxidized by heat treatment, is removed by etching, and an electrode terminal 9 is formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製法に関す
る。さらに詳しくは、集積回路装置(以下、ICとい
う)の回路素子として他の回路素子に接続されるキャパ
シタを有する半導体装置の製法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device. More specifically, it relates to a method for manufacturing a semiconductor device having a capacitor connected to another circuit element as a circuit element of an integrated circuit device (hereinafter referred to as an IC).

【0002】[0002]

【従来の技術】ICの回路素子としてトランジスタなど
と接続されるキャパシタは、図5に示されるように、接
続されるトランジスタなどが設けられた半導体基板であ
るケイ素基板51上に誘電体となる酸化膜52を設け、その
上に重ねて不純物をドープした上部電極となるポリシリ
コン層53を設け、ポリシリコン層53上部に上部電極端子
となる金属層54を設けた構造を有している。
2. Description of the Related Art As shown in FIG. 5, a capacitor connected to a transistor or the like as a circuit element of an IC is an oxide serving as a dielectric on a silicon substrate 51 which is a semiconductor substrate on which the connected transistor or the like is provided. A film 52 is provided, a polysilicon layer 53 serving as an upper electrode doped with impurities is provided thereon, and a metal layer 54 serving as an upper electrode terminal is provided above the polysilicon layer 53.

【0003】この構造のキャパシタは、一方の電極部が
金属層54とポリシリコン層53とからなり、他方の電極
は、たとえばトランジスタのコレクタが形成されたケイ
素基板51であり、キャパシタが直接半導体回路と接続さ
れている。このキャパシタの両電極間に介在される誘電
体は他の工程との関連で通常酸化膜52が用いられる。こ
の酸化膜52の誘電率は小さいので、静電容量を大きくす
るためには、電極の面積を広くするか、または前記酸化
膜52の膜厚を薄くする必要がある。しかし電極の面積を
広くすればキャパシタ素子が大きくなりICの集積度が
上がらない。また酸化膜52の膜厚を薄くすると、キャパ
シタの耐圧性能が低下して放電しやすくなるとともに、
ICの製造段階でこの酸化膜にピンホールが発生しやす
くなるなどしてICの信頼性が低下し、30Å程度が限度
となる。
In a capacitor having this structure, one electrode portion is composed of a metal layer 54 and a polysilicon layer 53, and the other electrode is, for example, a silicon substrate 51 on which a collector of a transistor is formed. Connected with. The oxide film 52 is usually used as a dielectric material interposed between both electrodes of this capacitor in connection with other steps. Since the dielectric constant of the oxide film 52 is small, it is necessary to widen the area of the electrode or reduce the film thickness of the oxide film 52 in order to increase the capacitance. However, if the area of the electrode is widened, the capacitor element becomes large and the integration degree of the IC cannot be improved. Also, if the thickness of the oxide film 52 is reduced, the withstand voltage performance of the capacitor is reduced and discharge becomes easier, and at the same time,
At the manufacturing stage of IC, pinholes are easily generated in this oxide film, which lowers the reliability of IC, and the limit is about 30Å.

【0004】また、このキャパシタはケイ素基板51を一
方の電極として用いているので浮遊容量がのりやすい。
すなわち、ケイ素基板51上の他の回路素子の影響を受け
易く、正確な容量がえられないという欠点がある。
Further, since this capacitor uses the silicon substrate 51 as one of the electrodes, the stray capacitance tends to increase.
That is, there is a drawback in that an accurate capacitance cannot be obtained because of being easily influenced by other circuit elements on the silicon substrate 51.

【0005】[0005]

【発明が解決しようとする課題】前述のごとく、従来の
キャパシタは一方の電極としてケイ素基板51を用いるの
で、他の回路素子からの電気的影響を受けやすく、設計
どおりの正確な静電容量がえられない。また電極間の誘
電体として酸化ケイ素膜を用いているので、表面積を大
きくすることなしにはキャパシタの静電容量を大きくで
きないという問題がある。
As described above, since the conventional capacitor uses the silicon substrate 51 as one of the electrodes, it is easily affected by electrical effects from other circuit elements, and the accurate capacitance as designed cannot be obtained. I can't. Further, since the silicon oxide film is used as the dielectric between the electrodes, there is a problem that the capacitance of the capacitor cannot be increased without increasing the surface area.

【0006】一方、キャパシタを該キャパシタと接続さ
れる回路素子が形成された半導体基板表面に直接設けな
いで、フィールド絶縁膜など半導体回路素子と関係のな
い場所に下部電極、シリコンチッ化膜などの誘電率が大
きい誘電体膜、上部電極を積層してキャパシタを形成す
ることも考えられるが、下部電極を他の回路素子と接続
するために、下部電極に接続される電極端子を形成する
ばあい、つぎのような問題が生じる。すなわち、コンタ
クト孔を形成したのち、カバレジを改良するためリフロ
ーし(熱処理をしてコンタクト孔の角部を滑らかにす
る)、そののち、下部電極上に生成された酸化膜を除去
するため、フッ酸などでエッチング処理するが、これら
処理液は通常酸化ケイ素膜をエッチングするがチッ化ケ
イ素膜をエッチングしにくい。そのためチッ化ケイ素膜
の突出部ができ、電極配線と下部電極との接続が不充分
になるという問題がある。
On the other hand, the capacitor is not directly provided on the surface of the semiconductor substrate on which the circuit element connected to the capacitor is formed, but the lower electrode, the silicon nitride film, or the like is formed at a place unrelated to the semiconductor circuit element such as a field insulating film. It may be possible to form a capacitor by laminating a dielectric film having a large dielectric constant and an upper electrode, but in the case of forming an electrode terminal connected to the lower electrode in order to connect the lower electrode to another circuit element, , The following problems occur. That is, after forming the contact hole, reflow is performed to improve the coverage (heat treatment is performed to smooth the corner portion of the contact hole), and then the oxide film formed on the lower electrode is removed to remove the fluorine. Although an etching treatment is performed with an acid or the like, these treatment liquids usually etch the silicon oxide film, but it is difficult to etch the silicon nitride film. Therefore, there is a problem in that the silicon nitride film has a protruding portion and the connection between the electrode wiring and the lower electrode becomes insufficient.

【0007】本発明は、かかる問題を解消するためにな
されたものであり、浮遊容量がのらず、かつ、容量値を
増大しても集積度の向上が可能で、しかも、電極配線の
接続に支障をきたさないキャパシタを有する半導体装置
の製法を提供することを目的とする。
The present invention has been made in order to solve such a problem, has no stray capacitance, and can improve the degree of integration even if the capacitance value is increased. An object of the present invention is to provide a method for manufacturing a semiconductor device having a capacitor that does not hinder the operation.

【0008】[0008]

【課題を解決するための手段】本発明の製法は、半導体
基板に集積回路が形成され、該回路内で他の回路素子と
接続される、キャパシタを有する半導体装置の製法であ
って、前記半導体基板表面に設けられた絶縁膜上に下部
電極、チッ化ケイ素膜および上部電極を順次積層してパ
ターニングすることにより前記キャパシタ部を形成する
と共に、前記下部電極の電極端子を(a)前記下部電極
の電極端子形成部における前記下部電極上に設けられた
チッ化ケイ素膜と保護膜をエッチングしてコンタクト孔
を設け、(b)該コンタクト孔の側面に露出した前記チ
ッ化ケイ素膜をエッチングして凹所を形成し、(c)熱
処理により前記コンタクト孔の角部を滑らかにしてか
ら、該熱処理により前記下部電極膜上に生成した酸化膜
をエッチング除去し、(d)前記コンタクト孔内に前記
電極端子となる金属膜を設けることにより形成すること
を特徴としている。
A method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a capacitor in which an integrated circuit is formed on a semiconductor substrate and connected to other circuit elements in the circuit. A lower electrode, a silicon nitride film, and an upper electrode are sequentially laminated on an insulating film provided on a substrate surface and patterned to form the capacitor portion, and the electrode terminal of the lower electrode is (a) the lower electrode. Etching the silicon nitride film and the protective film provided on the lower electrode in the electrode terminal forming part to form a contact hole, and (b) etching the silicon nitride film exposed on the side surface of the contact hole. After forming a recess and smoothing the corners of the contact hole by (c) heat treatment, the oxide film formed on the lower electrode film by the heat treatment is removed by etching. (D) is characterized by the formation by providing the electrode terminals become the metal film in the contact hole.

【0009】[0009]

【作用】本発明の半導体装置の製法によれば、他の回路
素子に接続されるキャパシタを半導体基板の絶縁膜上に
下部電極、チッ化ケイ素膜および上部電極を積層して形
成しているため、基板上の他の素子から電気的影響を受
けず、設計通りの安定した静電容量を有するキャパシタ
をうることができると共に、キャパシタの誘電体膜とし
て誘電率の大きいチッ化ケイ素を採用することができ、
電極の表面積を大きくすることなく、キャパシタの静電
容量を大きくすることができる。さらに、下部電極の接
続配線のコンタクト孔を設けたのち、チッ化ケイ素膜の
露出部分をエッチングしてから熱処理し、そののち酸化
膜を除去しているため、接続配線用の電極端子は断線の
おそれがなく形成され、確実に素子間接続ができ、信頼
性の高い半導体装置がえられる。
According to the method of manufacturing a semiconductor device of the present invention, a capacitor connected to another circuit element is formed by laminating a lower electrode, a silicon nitride film and an upper electrode on an insulating film of a semiconductor substrate. , It is possible to obtain a capacitor having stable capacitance as designed without being electrically affected by other elements on the substrate, and adopting silicon nitride having a large dielectric constant as the dielectric film of the capacitor. Can
The capacitance of the capacitor can be increased without increasing the surface area of the electrodes. Furthermore, after the contact hole of the connection wiring of the lower electrode is provided, the exposed portion of the silicon nitride film is etched and then heat-treated, and then the oxide film is removed. It is possible to obtain a highly reliable semiconductor device which is formed without fear, allows reliable connection between elements.

【0010】[0010]

【実施例】つぎに図面を参照しながら本発明のキャパシ
タの製法を説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing the capacitor of the present invention will be described below with reference to the drawings.

【0011】図1は本発明の製法によって作製されたI
Cのキャパシタ部分の一例を示す断面図、図2は本発明
の製法の一実施例である製法のうち、図1におけるキャ
パシタ部を形成する工程を示す工程図、図3は本発明の
製法の一実施例である製法のうち、図1における下部電
極の端子部を形成する工程を示す工程図、図4は本発明
の製法によって作製されたIC用キャパシタの他の例を
示す要部断面図である。
FIG. 1 shows I prepared by the manufacturing method of the present invention.
2 is a cross-sectional view showing an example of the capacitor portion of C, FIG. 2 is a process diagram showing a step of forming the capacitor part in FIG. 1 in the manufacturing method which is one embodiment of the manufacturing method of the present invention, and FIG. 3 is a manufacturing method of the present invention. 1 is a process diagram showing a step of forming a terminal portion of a lower electrode in a manufacturing method which is one embodiment, and FIG. 4 is a sectional view showing an essential part of another example of an IC capacitor manufactured by the manufacturing method of the present invention. Is.

【0012】まず、本発明の製法によって作製されるキ
ャパシタの一例について説明する。
First, an example of a capacitor manufactured by the manufacturing method of the present invention will be described.

【0013】図1において、1はキャパシタ部であり、
2はキャパシタ部1のポリシリコン層で形成される下部
電極(以下、ポリシリコン層という)3用の端子部であ
る。
In FIG. 1, 1 is a capacitor part,
Reference numeral 2 is a terminal portion for a lower electrode (hereinafter referred to as a polysilicon layer) 3 formed of the polysilicon layer of the capacitor portion 1.

【0014】キャパシタ部1および端子部2は、ともに
半導体基板となるケイ素基板4上に、フィールド酸化膜
5を介して形成されている。したがって、キャパシタ部
1および端子部2はともに同一基板上の他の素子から電
気的影響を受けず、計画どおりの容量値が正確にえられ
る。
The capacitor portion 1 and the terminal portion 2 are both formed on a silicon substrate 4 which is a semiconductor substrate with a field oxide film 5 interposed therebetween. Therefore, both the capacitor section 1 and the terminal section 2 are not electrically affected by other elements on the same substrate, and the capacitance value as planned can be obtained accurately.

【0015】なお、キャパシタ部1における誘電体には
誘電率が大きいチッ化ケイ素膜6を用いているため、大
きい容量値をうることができる。つぎに前記キャパシタ
部の製法を説明する。
Since the silicon nitride film 6 having a large dielectric constant is used as the dielectric in the capacitor section 1, a large capacitance value can be obtained. Next, a method of manufacturing the capacitor section will be described.

【0016】図2(a)に示すごとく、半導体基板上に
設けられた、たとえば酸化ケイ素やチッ化ケイ素などか
らなる絶縁膜上にキャパシタの下部電極をポリシリコン
膜やシリサイドなどを用いて設ける。具体例としてはケ
イ素基板4の一表面上に、熱酸化法などにより、二酸化
ケイ素からなるフィールド酸化膜5を形成し、フィール
ド酸化膜5の上面に下部電極たるポリシリコン層3を形
成する。ついでポリシリコン層3にホスフィン(P
3 )などの雰囲気の下で不純物を拡散させた。しかる
のち、マスキングを施してポリシリコン層3をエッチン
グすることにより、端子部をも考慮したキャパシタの所
望パターンの下部電極を設ける。
As shown in FIG. 2A, a lower electrode of a capacitor is provided by using a polysilicon film or silicide on an insulating film made of, for example, silicon oxide or silicon nitride provided on a semiconductor substrate. As a specific example, a field oxide film 5 made of silicon dioxide is formed on one surface of a silicon substrate 4 by a thermal oxidation method or the like, and a polysilicon layer 3 serving as a lower electrode is formed on the upper surface of the field oxide film 5. Then, a phosphine (P
Impurities were diffused under an atmosphere such as H 3 ). Then, the polysilicon layer 3 is masked and etched to form a lower electrode having a desired pattern of the capacitor in consideration of the terminal portion.

【0017】つぎに、図2(b)に示すごとく、下部電
極上にチッ化ケイ素からなる誘電体膜を積層する。具体
例としては、CVD法によって基板4の表面全面に誘電
体膜を構成するSi3 4 膜6を積層した。
Next, as shown in FIG. 2B, a dielectric film made of silicon nitride is laminated on the lower electrode. As a specific example, a Si 3 N 4 film 6 forming a dielectric film was laminated on the entire surface of the substrate 4 by the CVD method.

【0018】そして、図2(c)、(d)に示すごと
く、たとえば酸化ケイ素膜、SOG膜などからなる保護
膜をたとえばCVD法、塗布法などにより全面に積層
し、キャパシタを形成する上部電極の大きさに相当する
開口部を、たとえばフッ酸などによるエッチングにより
設け、たとえばAl−Si、ポリシリコンなどからなる
上部電極を設ける。この保護膜は開口部を設けるため、
誘電体膜であるチッ化ケイ素膜と選択的にエッチングす
る必要があり、チッ化ケイ素膜とエッチング特性の異な
る材料で積層される。具体例としては前記Si3 4
6の上面に保護膜たるSiO2 膜7をCVD法によって
形成した。しかるのちに、図2(d)に示すように、前
記SiO2 膜7の上面に上部電極用のパターニングを施
してエッチングすることにより開口部を設け、開口底部
に露出したSi3 4 膜6にスパッタ法により上部電極
用端子を構成するアルミニウムなどからなる金属膜8を
形成した。
Then, as shown in FIGS. 2 (c) and 2 (d), a protective film made of, for example, a silicon oxide film or an SOG film is laminated on the entire surface by, for example, a CVD method or a coating method to form an upper electrode for forming a capacitor. Is provided by etching with, for example, hydrofluoric acid, and an upper electrode made of, for example, Al—Si, polysilicon, or the like is provided. Since this protective film has an opening,
It is necessary to selectively etch the silicon nitride film, which is a dielectric film, and the silicon nitride film and the silicon nitride film are laminated with a material having different etching characteristics. As a specific example, a SiO 2 film 7 as a protective film is formed on the upper surface of the Si 3 N 4 film 6 by a CVD method. After that, as shown in FIG. 2D, the upper surface of the SiO 2 film 7 is patterned and etched for the upper electrode to form an opening, and the Si 3 N 4 film 6 exposed at the bottom of the opening 6 is formed. Then, a metal film 8 made of aluminum or the like, which constitutes the upper electrode terminal, was formed by sputtering.

【0019】以上の工程によってキャパシタ部1が形成
される。つぎに下部電極用の端子部2の形成法を説明す
る。
The capacitor portion 1 is formed by the above steps. Next, a method of forming the terminal portion 2 for the lower electrode will be described.

【0020】下部電極用端子部2は前記キャパシタ部1
と別の場所で下部電極と他の回路素子とを接続するため
に、接続配線を設けるためのものである。下部電極用端
子部2はキャパシタ部1と別の場所に形成されるが、前
記キャパシタ部1の形成と同時に積層された下部電極、
チッ化ケイ素膜、保護膜の積層部分で下部電極を露出さ
せて形成される。まず、図3(e)に示すごとく、リア
クティブイオンエッチング法(以下、RIE法という)
などにより保護膜7およびチッ化ケイ素膜6をエッチン
グしてコンタクト孔2aを形成し、下部電極3を露出さ
せる。具体例としては、RIE法により所定パターンに
SiO2 膜7およびSi3 4 膜6をエッチング除去し
て、端子部2用のコンタクト孔2aを形成した。
The lower electrode terminal portion 2 is the capacitor portion 1
This is for providing a connection wiring for connecting the lower electrode to another circuit element at another place. The lower electrode terminal portion 2 is formed at a different location from the capacitor portion 1, but the lower electrode is laminated at the same time as the formation of the capacitor portion 1,
It is formed by exposing the lower electrode at the laminated portion of the silicon nitride film and the protective film. First, as shown in FIG. 3E, a reactive ion etching method (hereinafter referred to as RIE method)
The protective film 7 and the silicon nitride film 6 are etched by, for example, to form the contact hole 2a, and the lower electrode 3 is exposed. As a specific example, the SiO 2 film 7 and the Si 3 N 4 film 6 were removed by etching in a predetermined pattern by the RIE method to form the contact hole 2a for the terminal portion 2.

【0021】つぎに、チッ化ケイ素膜6をエッチングす
る熱リン酸などのエッチング液でチッ化ケイ素膜6をエ
ッチングし、図3(f)に示されるように凹所2bを形
成する。具体例としては100 〜150 ℃程度の熱リン酸中
に基板4を40〜80分間浸漬して処理した。このとき、ポ
リシリコン層3およびSiO2 膜7は熱リン酸によって
は溶解されにくい。したがって、前記コンタクト孔2a
の内側面に露出したSi3 4 膜6のみがわずかに溶解
し、図3(f)に示すごとく凹所2bが形成された。
Next, the silicon nitride film 6 is etched with an etching solution such as hot phosphoric acid for etching the silicon nitride film 6 to form a recess 2b as shown in FIG. 3 (f). As a specific example, the substrate 4 was immersed in hot phosphoric acid at about 100 to 150 ° C. for 40 to 80 minutes for treatment. At this time, the polysilicon layer 3 and the SiO 2 film 7 are not easily dissolved by hot phosphoric acid. Therefore, the contact hole 2a
Only the Si 3 N 4 film 6 exposed on the inner surface of the was slightly dissolved, and a recess 2b was formed as shown in FIG. 3 (f).

【0022】つぎに、電極膜の断線を防止するため、コ
ンタクト孔2aのエッジ部2cを滑らかにすべく熱処理
をしてリフローする(図3(g)参照)。引き続き熱処
理により下部電極3に生成された酸化膜を除去するた
め、たとえばフッ酸などで酸化膜をエッチングする(図
3(h)参照)。この際、エッチング液ではチッ化ケイ
素膜6はエッチングされにくく、前工程でチッ化ケイ素
膜6のみをエッチングして凹所2bを形成しているた
め、突出部は生じない。具体例としては、基板4を900
〜950 ℃で約30分間保持してリフローを行った。そうす
ることにより、図3(g)に示すようにSiO2 のコン
タクト孔2aの角部分2cが溶けて滑らかになった。引
き続きフッ酸で0.5 〜2分間の処理を行った。その結果
コンタクト孔2aの底部にポリシリコン層3を露出させ
るときにも、なめらかなコンタクト孔2aの周縁および
底部が維持され、図3(i)に示される電極端子9用金
属膜(アルミニウムなどからなる)を形成したときに断
線などの不具合が防止された。
Next, in order to prevent disconnection of the electrode film, heat treatment is performed to smooth the edge portion 2c of the contact hole 2a and reflow is performed (see FIG. 3 (g)). Subsequently, in order to remove the oxide film formed on the lower electrode 3 by heat treatment, the oxide film is etched with, for example, hydrofluoric acid (see FIG. 3H). At this time, the silicon nitride film 6 is hard to be etched by the etching liquid, and only the silicon nitride film 6 is etched in the previous step to form the recess 2b, so that no protrusion is formed. As a specific example, the substrate 4 is 900
Reflow was carried out by holding at ~ 950 ° C for about 30 minutes. By doing so, the corner portion 2c of the SiO 2 contact hole 2a was melted and smoothed as shown in FIG. Subsequently, treatment with hydrofluoric acid was performed for 0.5 to 2 minutes. As a result, even when the polysilicon layer 3 is exposed at the bottom of the contact hole 2a, the smooth periphery and bottom of the contact hole 2a are maintained, and the metal film for the electrode terminal 9 shown in FIG. When it is formed, problems such as disconnection were prevented.

【0023】ついで、アルミニウム、Al−Si、Al
−Si−Cuなどの金属膜を蒸着法、スパッタリング法
などにより設け、エッチングして接続配線用の電極端子
9を設け、他の回路素子と接続する。具体例としては蒸
着法によりアルミニウム膜を7000〜10000 Å成膜し、ド
ライエッチングによりパターニングして上部電極を設け
た。
Then, aluminum, Al--Si, Al
A metal film of —Si—Cu or the like is provided by a vapor deposition method, a sputtering method, or the like, and is etched to provide an electrode terminal 9 for connection wiring, which is connected to another circuit element. As a specific example, an aluminum film having a thickness of 7,000 to 10,000 Å was formed by a vapor deposition method and patterned by dry etching to provide an upper electrode.

【0024】以上により、IC用キャパシタの下部電極
3用端子部2と他の回路素子との接続がなされ、集積回
路装置内に図1に示されるIC用キャパシタが完成す
る。
As described above, the lower electrode 3 terminal portion 2 of the IC capacitor is connected to other circuit elements, and the IC capacitor shown in FIG. 1 is completed in the integrated circuit device.

【0025】図4には、本発明の他の実施例に係わる形
成法によるキャパシタ部11が示されている。このキャパ
シタ部11は、前記実施例におけるもの(図1および図2
(d)参照)とは、チッ化ケイ素膜6の上面に第2ポリ
シリコン層12を形成したうえに、端子用の金属膜10が形
成される点で異なる。かかる構造によればエッチングに
よって第2ポリシリコン層12の面積を設定しうるため、
容易に、かつ精度よく設計値どおりの容量値をうること
ができる。
FIG. 4 shows a capacitor portion 11 formed by a forming method according to another embodiment of the present invention. This capacitor unit 11 is the same as that in the above-described embodiment (see FIGS. 1 and 2).
(See (d)) is different in that the second polysilicon layer 12 is formed on the upper surface of the silicon nitride film 6 and the metal film 10 for terminals is formed. With this structure, the area of the second polysilicon layer 12 can be set by etching,
It is possible to easily and accurately obtain the capacitance value as designed.

【0026】[0026]

【発明の効果】本発明の製法によれば、キャパシタに浮
遊容量の影響がなく、設計どおりの容量値をうることが
でき、しかもキャパシタ面積が大きくならないため、集
積度の向上も達成できる。さらに、キャパシタの下部電
極の接続配線も信頼性が高く形成でき、高品質のIC用
キャパシタを有する半導体装置をうることができる。
According to the manufacturing method of the present invention, the stray capacitance does not affect the capacitor, the capacitance value as designed can be obtained, and the area of the capacitor does not increase, so that the degree of integration can be improved. Further, the connection wiring of the lower electrode of the capacitor can be formed with high reliability, and a semiconductor device having a high quality IC capacitor can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の製法の一実施例によって作製されたI
C用キャパシタ部分の一例を示す断面説明図である。
FIG. 1 is an I prepared by an embodiment of the manufacturing method of the present invention.
It is a section explanatory view showing an example of a capacitor part for C.

【図2】本発明の製法の一実施例である製法のうちキャ
パシタ部を形成する工程を示す工程図である。
FIG. 2 is a process drawing showing a step of forming a capacitor portion in the manufacturing method which is an embodiment of the manufacturing method of the present invention.

【図3】本発明の製法の一実施例である製法のうち下部
電極の端子部を形成する工程を示す工程図である。
FIG. 3 is a process drawing showing a step of forming a terminal portion of a lower electrode in the manufacturing method which is an embodiment of the manufacturing method of the present invention.

【図4】本発明の製法の他の実施例によって作製された
IC用キャパシタ部の例を示す要部断面説明図である。
FIG. 4 is an explanatory cross-sectional view of essential parts showing an example of an IC capacitor part manufactured by another embodiment of the manufacturing method of the present invention.

【図5】従来のIC用キャパシタの一例を示す断面図で
ある。
FIG. 5 is a cross-sectional view showing an example of a conventional IC capacitor.

【符号の説明】[Explanation of symbols]

1 キャパシタ部 2 端子部 2a コンタクト孔 3 下部電極(ポリシリコン層) 4 ケイ素基板 5 フィールド酸化膜 6 チッ化ケイ素膜 8 上部電極 9 電極端子 1 Capacitor Part 2 Terminal Part 2a Contact Hole 3 Lower Electrode (Polysilicon Layer) 4 Silicon Substrate 5 Field Oxide Film 6 Silicon Nitride Film 8 Upper Electrode 9 Electrode Terminal

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板に集積回路が形成され、該回
路内で他の回路素子と接続される、キャパシタを有する
半導体装置の製法であって、前記半導体基板表面に設け
られた絶縁膜上に下部電極、チッ化ケイ素膜および上部
電極を順次積層してパターニングすることにより前記キ
ャパシタ部を形成すると共に、前記下部電極の電極端子
を(a)前記下部電極の電極端子形成部における前記下
部電極上に設けられたチッ化ケイ素膜と保護膜をエッチ
ングしてコンタクト孔を設け、(b)該コンタクト孔の
側面に露出した前記チッ化ケイ素膜をエッチングして凹
所を形成し、(c)熱処理により前記コンタクト孔の角
部を滑らかにしてから、該熱処理により前記下部電極膜
上に生成した酸化膜をエッチング除去し、(d)前記コ
ンタクト孔内に前記電極端子となる金属膜を設けること
により形成する半導体装置の製法。
1. A method of manufacturing a semiconductor device having a capacitor, in which an integrated circuit is formed on a semiconductor substrate and connected to other circuit elements in the circuit, the method comprising: forming an insulating film on a surface of the semiconductor substrate. The lower electrode, the silicon nitride film and the upper electrode are sequentially laminated and patterned to form the capacitor portion, and the electrode terminal of the lower electrode is formed on the lower electrode in the electrode terminal forming portion of the lower electrode (a). The silicon nitride film and the protective film provided on the substrate are etched to form contact holes, (b) the silicon nitride film exposed on the side surfaces of the contact holes is etched to form recesses, and (c) heat treatment is performed. After smoothing the corners of the contact hole by etching, the oxide film formed on the lower electrode film by the heat treatment is removed by etching. A method of manufacturing a semiconductor device, which is formed by providing a metal film to be an electrode terminal.
JP30375692A 1992-11-13 1992-11-13 Semiconductor device manufacturing method Expired - Lifetime JP2761334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP30375692A JP2761334B2 (en) 1992-11-13 1992-11-13 Semiconductor device manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30375692A JP2761334B2 (en) 1992-11-13 1992-11-13 Semiconductor device manufacturing method

Publications (2)

Publication Number Publication Date
JPH06151707A true JPH06151707A (en) 1994-05-31
JP2761334B2 JP2761334B2 (en) 1998-06-04

Family

ID=17924899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30375692A Expired - Lifetime JP2761334B2 (en) 1992-11-13 1992-11-13 Semiconductor device manufacturing method

Country Status (1)

Country Link
JP (1) JP2761334B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019208053A (en) * 2017-07-26 2019-12-05 株式会社村田製作所 Capacitor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019208053A (en) * 2017-07-26 2019-12-05 株式会社村田製作所 Capacitor
JP2021101480A (en) * 2017-07-26 2021-07-08 株式会社村田製作所 Capacitor
US11217395B2 (en) 2017-07-26 2022-01-04 Murata Manufacturing Co., Ltd. Capacitor
US11587738B2 (en) 2017-07-26 2023-02-21 Murata Manufacturing Co., Ltd. Capacitor

Also Published As

Publication number Publication date
JP2761334B2 (en) 1998-06-04

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