JPS63119579A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPS63119579A JPS63119579A JP26684086A JP26684086A JPS63119579A JP S63119579 A JPS63119579 A JP S63119579A JP 26684086 A JP26684086 A JP 26684086A JP 26684086 A JP26684086 A JP 26684086A JP S63119579 A JPS63119579 A JP S63119579A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- active layer
- groove
- gate electrode
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 abstract description 34
- 239000002184 metal Substances 0.000 abstract description 10
- 239000011229 interlayer Substances 0.000 abstract description 8
- 239000010408 film Substances 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 230000007547 defect Effects 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 229920005591 polysilicon Polymers 0.000 description 10
- 238000005530 etching Methods 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012299 nitrogen atmosphere Substances 0.000 description 2
- 235000003325 Ilex Nutrition 0.000 description 1
- 241000209035 Ilex Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 230000002940 repellent Effects 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 102220043690 rs1049562 Human genes 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
技術分野
本発明は薄膜トランジスター（ＴＰＴ）に関し、よシ詳
しくはトランジスターの活性層以外の不用薄膜を残し、
平坦なデバイス構成とした薄膜トランジスターに係る。[Detailed Description of the Invention] Technical Field The present invention relates to a thin film transistor (TPT), and more particularly, to a thin film transistor (TPT) that leaves unnecessary thin films other than the active layer of the transistor.
It relates to a thin film transistor with a flat device configuration.
従来技術
一般に、薄膜トランジスター（ＴＰＴ）は絶縁性基板上
に半導体薄膜を形成し、その薄膜中にＭＯＳ型もしくは
ＭＩＳ型のトランジスターを形成したものであシ、能動
素子の基本となシ、各種デバイスに応用されている。Conventional technology In general, a thin film transistor (TPT) is a semiconductor thin film formed on an insulating substrate and a MOS or MIS type transistor formed in the thin film.It is a basic active element and is used in various devices. It is applied to.
従来、このようなＴＰＴは、第２図に示されるように、
ガラス、セラミック等の絶縁性基板１上に減圧Ｃ’ＶＤ
＠またはプラズマＣＶＤ法によシポリシリコンまたはア
モルファスシリコンからなる半導体薄膜を形成し、この
薄膜のうち活性層２となるべき部分管残して活性層２以
外の不用部をなす薄膜をエツチング除去し、次いで活性
Ｒ２上にゲート電極３を形成した後、層間絶縁層４およ
びＡ７電極５を順次積層して形成されるものである。Conventionally, such a TPT, as shown in FIG.
Reduced pressure C'VD on an insulating substrate 1 made of glass, ceramic, etc.
A semiconductor thin film made of polysilicon or amorphous silicon is formed by @ or plasma CVD method, and the thin film forming unnecessary parts other than the active layer 2 is removed by etching, leaving a portion of this thin film that is to become the active layer 2. Next, after forming a gate electrode 3 on the active R2, an interlayer insulating layer 4 and an A7 electrode 5 are sequentially laminated.
しかしながら、このようにして得られるＴＰＴは第２図
に示されるように、活性層２ｔｌ−残した部分が他の部
分よりも薄膜の厚さだけ突出した形状となるため、この
活性層２上に積層した層間絶縁層４がその形成をひろい
、さらにその上に形成されるＡ！電極（メタル電極）に
段切れ部１０が生じ、段切れ不良の原因となるという問
題点を有するものである。However, as shown in FIG. 2, the TPT obtained in this way has a shape in which the remaining portion of the active layer 2tl protrudes from the other portions by the thickness of the thin film. The laminated interlayer insulating layer 4 expands its formation, and A! is further formed thereon. This has a problem in that a step break portion 10 occurs in the electrode (metal electrode), causing a step break failure.
目 的
本発明の目的は上記した如き従来の問題点を解消するも
のであって、メタル電極の段切れ不要が生じないＴＰＴ
’ｉ提供することにある。Purpose The purpose of the present invention is to solve the above-mentioned conventional problems, and to provide a TPT that does not require cutting of metal electrodes.
'I am here to serve you.
構成
本発明は、絶縁性基板上に形成される薄膜トランジスタ
ーにおいて、トランジスターの活性層となるべき基板上
の半導体薄膜と不用部となる薄膜とを共に基板上に残存
させ、かつこれら薄膜を１μｍ以下の距離で離間させた
ことを特徴とするものである。Structure The present invention provides a thin film transistor formed on an insulating substrate, in which both the semiconductor thin film on the substrate, which is to become the active layer of the transistor, and the thin film, which is an unnecessary part, remain on the substrate, and these thin films have a thickness of 1 μm or less. It is characterized by being separated by a distance of .
以下に本発明を添付図面を参照して説明する。The invention will now be described with reference to the accompanying drawings.
第１図は本発明の一実施例を示すもので、逆スタガー構
造としたＴＰＴ’ｉ示す。第１図において、石英１．ｅ
イレツクス等の絶縁性基板１上には半導体薄膜が形成さ
れている。この薄膜は活性層２と不用部６とに溝７によ
って離間されている。この溝７はその間隔が１μｍ以下
され、ｓｉｏ、ｓが充填され、活性層２と絶縁されてい
る。FIG. 1 shows an embodiment of the present invention, and shows a TPT'i having an inverted staggered structure. In FIG. 1, quartz 1. e
A semiconductor thin film is formed on an insulating substrate 1 such as Ilex. In this thin film, the active layer 2 and the unnecessary part 6 are separated by a groove 7. The grooves 7 have an interval of 1 μm or less, are filled with sio and s, and are insulated from the active layer 2.
活性層２上にはゲート酸化膜９が、そしてその上にはゲ
ート電極３が形成されている。ゲート電極３が形成され
た活性層２および不用部６上には活性層２のゲート電極
３を挾んだ位置にコンタクトホールを有するようにして
層間絶縁層４が形成される。そして、この層間絶縁層４
およびコンタクトホール表面にはメタル電極としてのＡ
Ｊｆｉ極５が第１図に示されるようにゲート電極３の上
部を残して形成される。A gate oxide film 9 is formed on the active layer 2, and a gate electrode 3 is formed thereon. An interlayer insulating layer 4 is formed on the active layer 2 on which the gate electrode 3 is formed and on the unnecessary portion 6 so as to have a contact hole at a position sandwiching the gate electrode 3 of the active layer 2 . Then, this interlayer insulating layer 4
and A as a metal electrode on the surface of the contact hole.
A Jfi pole 5 is formed leaving the upper part of the gate electrode 3 as shown in FIG.
本発明によるＴＰＴは上記のような構成となっておシ、
第２図に示した従来例のものと比べると、基板１上に形
成した半導体薄膜のうち、不用部６をなす薄膜を基板１
上に残存させ、かつ活性層２と不用部６との溝幅金１μ
ｍ以下とした点が異なフ、この点が本発明の特異な構成
をなすものでおる。この活性層２と不用部６との溝幅が
１μｍを越えると、間隙による凹みが上部構成に生じて
しまい、本発明の課題達成に支障をきたすおそれが生ず
る。好ましくは、この溝７内には上記実施例におけるよ
うに塗布型Ｓｉｎ。The TPT according to the present invention has the above-mentioned configuration, and
Compared to the conventional example shown in FIG.
A groove width of 1 μm between the active layer 2 and the unnecessary portion 6
The difference is that it is less than or equal to m, and this point constitutes a unique configuration of the present invention. If the width of the groove between the active layer 2 and the unnecessary portion 6 exceeds 1 μm, a depression will be formed in the upper structure due to the gap, which may impede the achievement of the object of the present invention. Preferably, this groove 7 is filled with coated type Sin as in the above embodiment.
形成剤７等により形成したＳＩＯ，’ｉ充填するように
する。Fill the SIO formed with the forming agent 7 or the like.
なお、第３図は第１図に示したＴＰＴの平面図を示し、
第１図はこの第３図のＡ−Ｂ線における断面図である。Note that FIG. 3 shows a plan view of the TPT shown in FIG.
FIG. 1 is a sectional view taken along line A-B in FIG. 3.
次に、第１図および第３図に示すＴＰＴを製造する場合
の一例をそのフローシートを示す第４図を参照して説明
する。Next, an example of manufacturing the TPT shown in FIGS. 1 and 3 will be described with reference to FIG. 4, which shows a flow sheet thereof.
第４図において、有機洗浄および酸洗浄をした石英基板
１に、温度６３０℃、圧力０．１２Ｔｏｒｒ、ガス混合
比５ＩＨ４／Ｎ２＝２５／１２０ＳＣＣＭなる条件で減
圧ＣＶＤにより半導体薄膜（ポリシリコン）ｔ−形成す
る（＆）。ポジタイプのフォトレジスト１１を用いてレ
ジストをパターニングしくｂ）、エッチャント（ＨＮＯ
，： Ｈ，０：ＨＦ＝１００ ： ４０ ： ６）で薄
膜を構成するポリシリコンをエツチングして活性層２と
不用部６とを分ける溝７ｉ形成しくＣ）、その後、レジ
ストを剥離する（ｄ）。次に、低粘度（５ｃｐ以下）の
塗布ｍ ｓｔｏ□形成剤（例えば、東京応化製ｏ ＣＤ
ｓｉ −ｓ ｏ ｏ ｏ ｏ ） ｔ−全面に塗布
する０これによフ溝７内も塗布型ＳｔＯ，形成剤で満さ
れる。In FIG. 4, a semiconductor thin film (polysilicon t- Form(&). Patterning the resist using positive type photoresist 11b), etchant (HNO)
, :H,0:HF=100:40:6) to form a groove 7i separating the active layer 2 and the unnecessary part 6 by etching the polysilicon constituting the thin film (C), and then peeling off the resist (d). ). Next, apply a low viscosity (5 cp or less) m sto□ forming agent (for example, Tokyo Ohka OCD
si - s o o o o ) t - Coat the entire surface 0 As a result, the inside of the groove 7 is also filled with the coating type StO and the forming agent.
このｓｔｏ□形成剤の塗布後、Ｎ２雰囲気中で、例えば
２８０℃、２０分：５００℃、３０分の熱処理を施し、
５ｉＯ１形成剤を８１０．８に変成させる（ｅ）。次Ｋ
、このＳｉｎｇ ８の層表面から活性層２および不用部
６をなす薄膜表面までの５ＩＯ２８’ｉエッチャント（
例えば、ＨＦ：Ｈ，Ｏ＝１ ： １０）でエツチングす
る（ｆ）。このエツチングのエンドポイントは半導体薄
膜の表面が表われ、エッチャントに対して撥水性が現わ
れる時点までとする。オーバーエツチングすると、溝γ
内のｓｉｏ、 ｓまでエツチングされてしまうようにな
る。After applying this sto□ forming agent, heat treatment is performed at 280°C for 20 minutes and at 500°C for 30 minutes in an N2 atmosphere,
5iO1 forming agent is denatured to 810.8 (e). Next K
, 5IO28'i etchant (
For example, etching is performed using HF:H,O=1:10) (f). The end point of this etching is defined as the point at which the surface of the semiconductor thin film appears and becomes water repellent to the etchant. If over-etched, the groove γ
Even the sio and s in the file are etched.
このようにして、溝γ内に５ｉｎ２８が充填され、活性
層２をなす薄膜および不用部６をなす薄膜の表面が連続
した平坦面となる。なお、溝７内にｓｉｏ、 ｓ ｔ−
充填しない場合にあっても溝の幅が１μ雷以下と極く狭
くされているので薄膜表面は実質的に平坦面とみなして
よい。In this way, the groove γ is filled with 5 in 28, and the surfaces of the thin film forming the active layer 2 and the thin film forming the unnecessary portion 6 become continuous and flat. In addition, in the groove 7, sio, st-
Even when not filled, the width of the groove is extremely narrow, less than 1 μm, so the thin film surface can be regarded as a substantially flat surface.
次に、ゲート酸化膜９を熱酸化法（温度１０２５℃、ｄ
ｒｙ Ｏ，，３００ＳＣＣＭ１３時間）によつて形成し
くｇ）、ゲート電極３となるポリシリコン１２を薄膜（
ポリシリコンからなる）と同一条件で積層する（ｈ）。Next, the gate oxide film 9 is formed using a thermal oxidation method (temperature: 1025°C, d
The polysilicon 12 that will become the gate electrode 3 is deposited as a thin film (g).
(consisting of polysilicon) under the same conditions (h).
ボジタイゾのフォトレジストを使用してレジス）？パタ
ーコンクシ（１）、ポリシリコン１１とゲート酸化膜８
の不用部を連続してエツチングする。エッチャントはポ
リシリコンについては（ｃ）工程で用いたものと同じも
のを、ゲート酸化膜については（ｆ）工程で用いたもの
と同じものを用いる。エンドポイントは見づらいので大
面積のものでモニタリングし、その時間エッチャントに
浸ｆｆｆる（ｊ）。レジストを剥離した後、ゲートをマ
スクとしてセルフアライメント方式で不純物を拡散する
（ｋ）。Regis using Boji Tyzo photoresist)? Patter concretion (1), polysilicon 11 and gate oxide film 8
Continuously etch the unnecessary parts. For the polysilicon, the same etchant used in step (c) is used, and for the gate oxide film, the same etchant used in step (f) is used. The end point is difficult to see, so monitor it with a large area and soak it in the etchant for that period of time (j). After removing the resist, impurities are diffused using a self-alignment method using the gate as a mask (k).
拡散法はイオン打込み、気相拡散等があるが、図示の例
では固相−固相拡散を用いた。すなわち、全面にＰ、０
．を含んだ塗布型ＳｔＯ，形成剤（例えば、東京応化製
ＰＳＧ Ｐ −５９２５０）をスピンコードし、２８
０℃、２０分：９００℃、１０分の熱処理全Ｎ２雰囲気
中で行い、熱処理後、エッチャント（ＨＦ ：Ｈ，Ｏ＝
１ ： １０ ）で塗布剤を全面エツチングすることに
よって拡散工程が終了する。この拡散工程でチャンネル
（ソース、ドレイン）が形成され、同時にゲート間のポ
リシリコンも低抵抗化される。層間絶縁層４は温度４２
５℃、圧力１． ＯＴ＠ｒｒ、ガス混合比イブの７オト
レジストヲ使用してレジストヲノクターニングし、エッ
チャント（ＨＦ ： Ｈ，Ｏ＝ １＝１０）でエツチン
グする工程（省略）ｔ−経てコンタクトホールが形成さ
れるＣ１）。最後にメタル電極としてＡＩを真空蒸着法
（析出真空度５Ｘ １０−’Ｔｏｒｒ ）で蒸着し、ポ
ジタイプの７オトレジストを使用してレジストをノぞタ
ーニングし、エッチャント（Ｈ，ＰＯ，： ＨＮＯｓ：
ＣＨ３ＣＯ０Ｈ：Ｈ２０＝１６：１：２：１）でエツ
チングする工程（省略）を経て、ＡＩ電極５が形成され
る（ｍ）。Diffusion methods include ion implantation, gas phase diffusion, etc., but solid phase-solid phase diffusion is used in the illustrated example. In other words, P, 0 on the entire surface
．． A coating type StO containing a forming agent (for example, PSG P-59250 manufactured by Tokyo Ohka Co., Ltd.) was spin-coded and
0°C, 20 minutes: Heat treatment at 900°C, 10 minutes in a total N2 atmosphere. After the heat treatment, etchant (HF:H,O=
The diffusion process is completed by etching the coating agent over the entire surface at a ratio of 1:10). This diffusion process forms channels (source, drain) and at the same time lowers the resistance of the polysilicon between the gates. The interlayer insulating layer 4 has a temperature of 42
5℃, pressure 1. OT@rr, the process of etching the resist using 7-oto-resist with a gas mixture ratio of Ib and etching with an etchant (HF: H, O = 1 = 10) (omitted) t - A contact hole is formed (C1) . Finally, AI was deposited as a metal electrode using a vacuum evaporation method (deposition vacuum degree 5×10-'Torr), and the resist was groove-turned using a positive type 7-otoresist, and an etchant (H, PO,: HNOs:
After an etching step (omitted) using CH3CO0H:H20=16:1:2:1), the AI electrode 5 is formed (m).
効果
以上のような本発明によれば、基板上に形成されるポリ
シリコンまたはアモルファスシリコンからなる半導体薄
膜のうち、活性層部分のみならず不用部をも活性層と１
μｍ以下の間隙を有して残存させたため、活性層をなす
薄膜が平坦面内に形成され、その上に順次積層された各
ＴＰＴ構成部材のうち最上層をなすメタル電極に段切れ
部が生じず、メタル配線の段切れ不良の発生が全く生じ
ず、歩留りのよいＴＰＴが得られるという効果金有する
。Effects According to the present invention as described above, not only the active layer portion but also the unused portion of the semiconductor thin film made of polysilicon or amorphous silicon formed on the substrate can be combined with the active layer.
Because the thin film forming the active layer was left with a gap of less than μm, a thin film forming the active layer was formed on a flat surface, and a step part was created in the metal electrode forming the top layer of each TPT component member laminated in sequence on top of the thin film. First, there is no occurrence of metal wiring breakage defects at all, and TPTs with high yields can be obtained.
第１図は本発明に係るＴＰＴの断面説明図である。
第２図は従来のＴＰＴの断面説明図である。
第３図は第１図のＴＰＴの平面説明図である。
第４図は第１図のＴＰＴを製造する場合の工程説明図で
ある。
１・・・基 板 ２・・・活性層３・・・ゲ
ート電極（ポリシリコン）
４・・・層間絶縁層
５・・・ｋｌ電極（メタル電極）
６・・・不用部 ７・・・溝８・・・８１０
． ９・・・ゲート酸化膜１０・・・段切
れ部 １１・・・フォトレジスト１２・・・ぼり
シリコン
特許出願人 株式会社 リ コ −
第１図
第２図
第３図
第４図FIG. 1 is an explanatory cross-sectional view of the TPT according to the present invention. FIG. 2 is an explanatory cross-sectional view of a conventional TPT. FIG. 3 is an explanatory plan view of the TPT shown in FIG. 1. FIG. 4 is a process explanatory diagram for manufacturing the TPT shown in FIG. 1. 1... Substrate 2... Active layer 3... Gate electrode (polysilicon) 4... Interlayer insulating layer 5... kl electrode (metal electrode) 6... Unused part 7... Groove 8...810
．． 9...Gate oxide film 10...Step cut portion 11...Photoresist 12...Bori silicon patent applicant Rico Co., Ltd. - Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
いて、トランジスターの活性層となるべき基板上の半導
体薄膜と不用部となる薄膜とを共に基板上に残存させ、
かつこれら薄膜を１μｍ以下の距離で離間させたことを
特徴とする薄膜トランジスター。1. In a thin film transistor formed on an insulating substrate, both the semiconductor thin film on the substrate which is to become the active layer of the transistor and the thin film which is to be an unnecessary part remain on the substrate,
A thin film transistor characterized in that these thin films are separated by a distance of 1 μm or less.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26684086A JPS63119579A (en) | 1986-11-07 | 1986-11-07 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26684086A JPS63119579A (en) | 1986-11-07 | 1986-11-07 | Thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63119579A true JPS63119579A (en) | 1988-05-24 |
Family
ID=17436388
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26684086A Pending JPS63119579A (en) | 1986-11-07 | 1986-11-07 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119579A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5996742A (en) * | 1993-06-28 | 1999-12-07 | Kone Oy | Elevator machinery |
| JP2005340771A (en) * | 2004-05-22 | 2005-12-08 | Samsung Sdi Co Ltd | Thin film transistor, method for manufacturing thin film transistor, plate display with thin film transitor, and method for manufacturing plate display |
-
1986
- 1986-11-07 JP JP26684086A patent/JPS63119579A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5996742A (en) * | 1993-06-28 | 1999-12-07 | Kone Oy | Elevator machinery |
| JP2005340771A (en) * | 2004-05-22 | 2005-12-08 | Samsung Sdi Co Ltd | Thin film transistor, method for manufacturing thin film transistor, plate display with thin film transitor, and method for manufacturing plate display |
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