JPS63298677A - Data gathering device - Google Patents

Abstract

PURPOSE:To sample whether or not a signal level varies with simple constitution by providing plural level variation storage circuits and a sampling circuit which receives their outputs as a data input. CONSTITUTION:The output signals of FFs 31 and 32 becomes '1' in response to the level variation of an input signal and becomes '0' with a clear pulse from a timing generating circuit 1. When a data gathering device for 0 1 variation detection is constituted, leading edge trigger types are used as the FFs 31 and 32 and when a data gathering device for 1 0 variation detection is constituted, trailing edge trigger types are used as the FFs 31 and 32. The outputs of the FFs 31 and 32 are ORed by a gate 4 and supplied as input data to the sampling circuit, but the data is sampled in synchronism with the sampling clock from the timing generating circuit 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data collection device, and more particularly to a device that periodically samples the presence or absence of a signal level change within a unit time.

(Prior Art) Conventional data acquisition devices such as logic analyzers sample signal levels periodically, and attempts have been made to detect changes in signal levels using this type of data acquisition device. In this case, as shown in Figure 6, the sampling data at time T (n) and the time T (n+1)
It was detected that the sampled data of the two were different.

(Problem to be Solved by the Invention) When trying to detect changes in signal level using the conventional data acquisition device described above, if a very high-speed sampling circuit is used, it is possible to Although detection was possible, this sampling circuit required the use of an element whose operating speed was more than an order of magnitude faster than the object to be measured. In particular, as shown in Figure 5, when the fact that the signal level has changed within a certain unit time is required, rather than the one time when the signal level changed, that fact is sampled for each unit time. There was a need for a simple device to accomplish this.

For example, tracing the execution path of a program on an information processing device by sampling the path information of the information processing device is an effective means for testing and debugging a program, but it is especially effective when changing signal levels. In the case of information processing equipment where interrupts are requested by
All that is needed is the fact that there is a change in signal level in a cycle, and there is a need for a device that simultaneously samples the presence or absence of a change in signal level for each pass cycle along with other path information.

An object of the present invention is to provide a device with a simple configuration that periodically samples the presence or absence of a change in signal level within a certain unit time.

(Means for Solving the Problems) FIG. 1 is a block diagram showing the basic configuration of the data acquisition device of the present invention when there are two level change storage circuits. The data collection device shown in the figure includes a plurality of level change storage circuits 31 and 32 that store changes in input signal levels, and a sampling circuit 2 whose output is used as data input.
Level change memory circuit with basic tarokku as input 31.32
The timing generation circuit 1 outputs clear pulses 101 and 102 to the templating circuit 2 and a sampling clock 103 to the templing circuit 2.

(Function) The reason why a plurality of level change memory circuits are required will be explained with reference to FIG. The level change memory circuit needs to be cleared once every sampling interval, but if there is only one level change memory circuit as shown in Figure 4, a change in level will not be detected while the level change memory circuit is cleared. I can't do it. However, if a plurality of level change memory circuits are used as shown in FIG. 1, even while one level change memory circuit is being cleared, a υ level change can be detected by other level change memory circuits.

(Embodiment) FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a waveform diagram of various signals in the circuit of FIG. 2. Second
The illustrated embodiment is an embodiment of the apparatus shown in FIG. The flip-flops 31 and 32 change their output signal to 611 due to a change in the level of the input signal, and change their output signal to 001 due to a clear pulse from the timing generation circuit 1. 0→
1 To make it a data collection device for detecting a change, flip-flops 31 and 32 should be of the rising edge trigger type, and 1→
To use it as a data acquisition device for O detection, the flip-flops 31 and 32 may be of the falling edge trigger type. The outputs of the flip-flops 31 and 32 are ORed by the gate 4 and become data input to the sampling circuit 2, and this data is sampled in synchronization with the sampling clock from the timing generation circuit 1. The sampling circuit 2 is composed of a counter and a memory, and can refer to external sampling information.

The timing generation circuit 1 is composed of a counter 11 and a decoder 12. As shown in FIG.
The decoder 12 sends a clear pulse to the flip-flop 31 when the value of the counter 11 is 11@, and the decoder 12 sends a clear pulse to the flip-flop 32 when the value of the counter 11 is 131. send. Furthermore, the lower 1 bit of the counter 11 is input to the sampling circuit 2.
This serves as the sampling clock for the

As described above, by sending clear pulses with different phases to the level change storage circuits 31 and 32, only one output of the level change storage circuits 31 and 32 at the sampling timing can be used as the data input of the sampling circuit 2. can be enabled and the other level change storage circuit can be cleared at the same time.

(Effects of the Invention) As described above, according to the present invention, there is an effect that a device that periodically samples the presence or absence of a signal level change within a certain unit time can be realized with a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of the data collection device of the present invention when there are two level change storage circuits, and FIG. 2 specifically shows the data collection device of the present invention shown in FIG. 3 is a waveform diagram showing various signals in the embodiment of FIG. 2, and FIG. 4 is a diagram of an incomplete data acquisition device used for explaining FIG. A block diagram, FIG. 5 is a diagram showing an example of sampling in the present invention,
FIG. 6 is a diagram showing a signal level change detection method using a conventional sampling circuit. In the figure, 1 is a timing generation circuit, 2 is a pull/pull circuit, 3, 31.32 is a level change storage circuit, 4 is an OR gate, 11 is a counter, 12 is a decoder, and 5 is the output of the level change storage circuit 31. 6 is an output signal of the level change storage circuit 32, 7 is an OR gate, and 4 is an output signal. Agent Patent Attorney Shinsuke Honjo Third cause

Claims (1)

[Claims] a plurality of level change memory circuits that store changes in input signal levels; a sampling circuit that uses the outputs of the plurality of level change memory circuits as data input; and a basic clock as input, and a plurality of level change memory circuits that use the outputs of the plurality of level change memory circuits as data inputs; 1. A data acquisition device comprising: a timing generation circuit that outputs clear pulses of mutually different phases to the sampling clock; and a timing generation circuit that outputs the sampling clock.