JP2818192B2 - Noise removal device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a noise elimination device that samples an input signal at a predetermined cycle and removes noise generated in the input signal.

(Prior Art) Many microcomputers and the like are provided with a noise elimination circuit for eliminating noise such as chattering of an input signal to prevent malfunction.

As such a noise removing circuit, for example, there is a circuit configured as shown in FIG.

In FIG. 6, an input signal is synchronized with a rising edge of a clock signal (CK) by a shift register including flip-flops (hereinafter referred to as "F / F") 1, 2, and 3 cascaded in three stages. Sample and hold. Sampled and held by each F / F1,2,3 and signals 1,2,3
Is supplied to the determination circuit 4. When all of the applied signals 1, 2, and 3 have the same level value, the determination circuit 4 sets the output determination signal to "0" and outputs at least one of the signals 1, 2, and 3.
If the two are different, the determination signal is given to the multiplexer 5 as "1". The multiplexer 5 selects the signal 1 that is the output of the F / F 1 when the determination signal of the “0” level is supplied, and supplies the signal 1 to the input of the F / F 6. Select the output signal held by / F6
Give to F / F6 input.

Thus, in the noise elimination circuit shown in FIG.
The input signal (signal 1) sampled and held by the F / F1 is input signal (signal 2, signal 3) sampled during a period of two cycles immediately before the signal 1 of the clock signal cycle (sampling cycle) is sampled. ),
The output signal up to that point is held, and if it matches, the signal 1 is output.

Accordingly, when the pulse width of the signal 1 obtained by sampling and quantizing the input signal during the sampling period is equal to or less than twice the sampling period, the pulse generated in the input signal is removed as noise, and the noise is removed. The obtained input signal is obtained as the output signal of F / F6.

For example, if the clock cycle is 1 μs and the input signal is 2 μs
In the case of a pulse signal having an s width, it operates at the timing shown in FIG. 7, the input signal is determined as noise and removed, and the output signal is in a state where the previous value is held.

On the other hand, if the input signal is a pulse signal having a pulse width of 3 μs, the operation is performed at the timing shown in FIG. 8, and the input signal is determined to be a normal signal and is obtained as an output signal.

Further, for example, when continuous noise occurs in the input signal in synchronization with the clock signal as shown in FIG. 9, the circuit operates at the timing as shown in FIG. In some cases, the output signal is determined as a certain pulse signal and is obtained as an output signal. This is because it is extremely difficult to capture a change in the input signal that is shorter than the sampling period in a method for removing noise by sampling the input signal. Therefore, in order to increase the accuracy of the noise elimination circuit, it is necessary to shorten the sampling period.

For example, with a sampling period of 1 μs, a pulse noise having a width of 200 ns may cause the above-mentioned problem. However, with a sampling period of 50 ns, such a problem does not occur.

(Problems to be Solved by the Invention) However, if a noise removal circuit with a short sampling period is to be configured according to the conventional configuration, the circuit configuration will be large-scale. That is, for example, when the noise elimination circuit shown in FIG. 6 is to be changed to a noise elimination circuit having a sampling period of 50 ns, a flip-flop for holding an input signal of 2 μs sampled every 50 ns is provided. You need 40. The number of flip-flops increases as the sampling period becomes shorter.

As described above, if the sampling period is shortened, noise can be removed with high accuracy. However, when the sampling period is shortened, a problem such as an increase in the circuit scale is caused.

Therefore, the present invention has been made in view of the above, and an object of the present invention is to provide a highly accurate noise elimination device without increasing the size of the configuration.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, a first invention monitors an input signal at a first cycle and makes the input signal longer than the first cycle. Input monitoring means for detecting whether or not a change has occurred at least once within a long second cycle; and operating in synchronization with the second cycle, wherein the input monitoring means detects a change in an input signal. Holding the output signal up to that time, and when the input monitoring means does not detect a change in the input means, outputs the input signal and removes noise having a cycle shorter than the second cycle from the input signal. And noise removing means.

The second invention monitors the input signal in a first cycle and detects whether the input signal has changed at least once in a second cycle longer than the first cycle. Monitoring means, storage means for holding a detection result of the input monitoring means, operating in synchronization with the second cycle, indicating that the input monitoring means or the storage means has detected a change in an input signal; The input monitoring means and the storage means output the input signal if the input monitoring means and the storage means have not detected a change in the input signal. And noise removal processing means for removing, from the input signal, noise having a cycle shorter than the second cycle including noise having a cycle longer than the second cycle defined by the number of detection results stored in the input signal.

(Operation) In the above-mentioned first configuration, the first invention monitors an input signal in a first cycle, detects a change in the input signal in a second cycle, and responds to the detection result. The output signal is determined so that noise having a maximum pulse width equal to the second period is removed from the input signal.

On the other hand, in the second configuration, the second invention is the first configuration.
By monitoring the input signal in the cycle of, a change in the input signal is detected in the second cycle, and the output signal is determined according to the detection result and the previous detection result. Noise longer than the period is removed from the input signal.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a noise elimination device according to one embodiment of the present invention. The noise elimination device of the embodiment shown in the figure monitors the change of the input signal by the first clock signal, and changes the output signal according to the change of the input signal within the cycle of the second clock signal. ing.

In FIG. 1, the noise elimination device includes four F / Fs 11, 12, 1
The input signal monitoring means is constituted by a circuit centered on the F / F 12, and the noise removal processing means is constituted by a circuit centered on the F / F 14 and the multiplexer 15. The storage means is constituted by the F / F13.

The F / F 11 samples the input signal in synchronization with the rising of the first clock signal (CK1). The first clock signal is a clock signal that determines a cycle of the noise removal processing. The output (signal 11) of the F / F 11 is logically operated by an exclusive OR (EXOR) gate 16 with the input signal. Also, signal 11
Is supplied to one input of a multiplexer 15.

The output of the EXOR gate 16 is supplied to the F / F 12 via a logical sum (OR) gate 17 having one input as an output of the F / F 12 and a logical product (AND) gate 18 having one input as a clear signal. Can be The F / F 12 sets and holds the output of the AND gate 18 in synchronization with the second clock signal (CK2) having a period much shorter than the period of the first clock signal. That is, F / F12
Is set to "1" when the level value sampled and held by the F / F 11 is different from the level value of the input signal. This allows the F / F12 to detect changes in the input signal during the input signal monitoring operation, and
It is output as a detection signal via 19.

Further, when the “1” level is set, the F / F 12 keeps holding the previous state until the clear signal becomes “0” level. When the clear signal becomes “0” level, the F / F 12 is cleared and reset. At this time, if the input signal changes, this change is supplied to the OR gate 19, bypassing the F / F 12 in the clear state, and the detection signal is output to the OR gate 19.
Output via 19.

In this way, the F / F 12 monitors the change of the input signal, and when the input signal changes during, for example, one cycle of the first clock signal (CK1), the detection signal is output at the timing shown in FIG. Is output. The detection signal output from the OR gate 19 is supplied to the F / F 13.

The F / F 13 captures the detection signal in synchronization with the rising of the first clock signal, and holds it until the first clock signal rises next. That is, the F / F 13 stores the change of the input signal for the past one cycle of the first clock signal. By providing such a storage unit, the maximum pulse width serving as noise to be removed can be made longer than the cycle of the first clock signal which is the processing cycle of the removal processing. On the other hand, when this storage means is not provided, the maximum pulse width which is the noise to be removed becomes equal to the processing cycle. The F / F 13 supplies the output (signal 13) to the multiplexer 15 via the OR gate 20 having one input to which the detection signal is supplied.

The multiplexer 15 selects the output signal output from the F / F 14 or the signal 11 based on the output (signal 20) of the OR gate 20. That is, the multiplexer 15 outputs the signal
When 20 is at the "0" level, the signal 1 is selected and applied to the F / F 14, and when it is at the "1" level, the output signal is selected and applied to the F / F 14.

The F / F 14 captures and holds the value selected and provided by the multiplexer 15 in synchronization with the first clock signal, and outputs the held value as an output signal. Therefore, only when both the detection signal and the signal 13 are at “0” level, the signal sampled and held by the F / F 11 is output as the output signal of the noise elimination device. In other cases, the state of the output signal up to that time is held. That is, at least one of the detection result of the first cycle of the first clock signal held in the F / F 13 and the detection signal output from the F / F 12 detects a change in the input signal. In the case shown, the noise removal processing is performed without changing the output signal.

In such a configuration, when a pulse signal shorter than twice the value of the cycle of the first clock signal as the processing cycle is generated in the input signal, as shown in the operation timing of FIG. Will change. In FIG. 3, since the input signal changes in the first cycle and the third cycle of the first clock signal (CK1), the input signal changes in synchronization with the processing of the first clock signal in the first to fourth cycles. If so,
A state in which a change in the input signal is detected. Therefore,
During this period, since the output signal is not changed, as shown in FIG. 3, in the output signal, the pulse signal is determined to be noise and removed, and the state of the input signal up to that point is shown.

On the other hand, the period of the first clock signal, which is the processing period, is 2
When a pulse signal longer than the doubled value is generated in the input signal, each signal changes as shown in the operation timing of FIG. In FIG. 4, the input signal does not change in the second and third cycles of the first clock signal, and therefore, in the third cycle of the first clock signal, there is no input signal. A change is detected. This allows
An input signal (signal 11) sampled by the F / F 11 is output as an output signal, and a pulse signal generated in the input signal is obtained as a regular input signal.

On the other hand, if a pulse signal shorter than the period of the first clock signal for processing synchronization is generated in the input signal, the fifth signal
Each signal changes as shown in the operation timing of the figure. In FIG. 5, since the input signal changes in each of the first to fourth cycles of the first clock signal, the input signal is changed in the processing cycle from the first to fifth cycles. A change is detected. Therefore, during this period, since the output signal is not changed, as shown in FIG. 5, the output signal is judged as the noise of the pulse signal and removed, thereby indicating the state of the input signal until then. .

Accordingly, in the conventional example shown in FIG. 9, pulse noise having a continuous short pulse width could not be removed in synchronization with the sampling period, whereas in the above-mentioned embodiment, FIG. Can be completely removed as shown in FIG.

As described above, by shortening the monitoring period (the period of the second clock signal) for monitoring a change in the input signal, it is possible to reliably remove noise having a shorter pulse width than the processing period generated in the input signal. Becomes possible. Further, by shortening the monitoring period, the circuit scale does not increase.

[Effects of the Invention] As described above, in the noise elimination device to which the present invention is applied, the input signal is monitored at the first cycle, and the change of the input signal within the second cycle is detected. Since the output signal is determined based on this detection result or this detection result and the previous detection result, noise with a short pulse width defined by the first cycle can be easily generated from the input signal with a small-scale configuration. And it becomes possible to remove it reliably. As a result, by shortening the first cycle of monitoring the input signal, it is possible to provide a noise removing device with higher accuracy than before, without increasing the size of the configuration.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a noise eliminator according to an embodiment of the present invention, FIGS. 2 to 5 are operation timing charts of the device shown in FIG. 1, and FIG. FIGS. 7 to 9 are timing charts showing the operation of the apparatus shown in FIG. 11, 12, 13, 14… Flip-flop 15… Multiplexer 16 to 20… Logic gate

Claims (2)

(57) [Claims] 1. An input monitoring means for monitoring an input signal at a first cycle and detecting whether the input signal has changed at least once in a second cycle longer than the first cycle. Operating in synchronism with the second period, when the input monitoring means detects a change in the input signal, holds the output signal up to that time, and the input monitoring means does not detect the change in the input signal A noise removing unit that outputs an input signal and removes noise having a cycle shorter than the second cycle from the input signal. 2. An input monitoring means for monitoring an input signal in a first cycle and detecting whether the input signal has changed at least once in a second cycle longer than the first cycle. A storage unit for holding a detection result of the input monitoring unit, and operating in synchronization with the second cycle, indicating that the input monitoring unit or the storage unit has detected a change in an input signal. , Hold the output signal up to that point,
If the input monitoring means and the storage means indicate that the change of the input signal has not been detected, an input signal is output, and the input signal is defined by the number of detection results stored in the storage means. Noise removal processing means for removing noise having a cycle shorter than the second cycle including noise having a cycle longer than the second cycle from an input signal.