JPS6329818B2 - - Google Patents

Info

Publication number
JPS6329818B2
JPS6329818B2 JP56099439A JP9943981A JPS6329818B2 JP S6329818 B2 JPS6329818 B2 JP S6329818B2 JP 56099439 A JP56099439 A JP 56099439A JP 9943981 A JP9943981 A JP 9943981A JP S6329818 B2 JPS6329818 B2 JP S6329818B2
Authority
JP
Japan
Prior art keywords
type
terminals
terminal
semiconductor element
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56099439A
Other languages
Japanese (ja)
Other versions
JPS582039A (en
Inventor
Izumi Tanaka
Hiroshi Hirao
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9943981A priority Critical patent/JPS582039A/en
Publication of JPS582039A publication Critical patent/JPS582039A/en
Publication of JPS6329818B2 publication Critical patent/JPS6329818B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Description

【発明の詳細な説明】 本発明は半導体基板の試験方法に係り、特に複
数種類の素子が形成された半導体基板の自動試験
方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for testing a semiconductor substrate, and more particularly to an automatic method for testing a semiconductor substrate on which a plurality of types of elements are formed.

半導体装置の製造工程において、素子形成工程
を終了した半導体基板を個々の素子に切断分離す
る前に、基板上に形成された総ての素子の試験を
行なう。この基板の試験は周知の如く試験装置の
移動台上に被試験試料の基板を載置し正確に位置
合わせを行なつた後、素子表面に設けられたパツ
ドに試験装置から導出されたプローバーの測定用
探針の先端を接触せしめ、予め作成された試験プ
ログラムに従つて各種試験を行なつて素子の良否
を判定する。次いで移動台を移動することにより
上記操作をすべての素子について繰り返し、全素
子について試験を行なう。
In the manufacturing process of a semiconductor device, before a semiconductor substrate that has undergone an element formation process is cut and separated into individual elements, all elements formed on the substrate are tested. As is well known, in this board test, the test sample board is placed on the moving table of the test equipment and aligned accurately, and then a prober drawn out from the test equipment is placed on a pad provided on the element surface. The tip of the measuring probe is brought into contact with the device, and various tests are performed according to a test program created in advance to determine the quality of the device. Next, the above operation is repeated for all the elements by moving the movable table, and the test is performed on all the elements.

以上の操作はすべて自動的に行なわれるのであ
るが、同一基板上に2種類以上の素子が形成され
ているときは、素子の種類により試験プログラム
を変更せねばならないため、基板の試験を前述し
たように自動的に行なうことができない。このよ
うな事態は使用者の要求する情報を格納するマス
クROMの生産工程において比較的少量の発注を
受けたときや、半導体装置の研究・開発段階等で
生じるものである。
All of the above operations are performed automatically, but when two or more types of elements are formed on the same board, the test program must be changed depending on the type of element, so the board test is performed as described above. It cannot be done automatically like this. Such situations occur when relatively small orders are received in the production process of mask ROMs that store information requested by users, or during the research and development stage of semiconductor devices.

本発明はこのような場合においても同一基板上
に作成された複数種類の素子の種別を自動的に識
別し得る半導体基板の改良された構成を提供する
ことを目的とし、この目的は本発明において、半
導体基板の表面に、少なくとも1種類の半導体素
子とともに、この半導体素子の種別に対応して判
定用素子を配設し、この判定用素子を、上記半導
体素子表面に設けられた電源端子、ソース端子、
および複数個の出力端子の配設位置に対応する位
置にそれぞれ測定用パツドを具え、上記電源端子
およびソース端子の配設位置と同じ位置に測定用
パツドを半導体素子の種別を識別するための識別
信号を供給する入力用端子、残りの測定用パツド
を検知端子とし、上記入力用端子間を上記検知端
子の中から半導体素子の種別に対応して選択され
た1つを介して接続しておき、上記入力端子に識
別信号を印加した時、この識別信号が検出される
検知端子の位置から、対応する半導体素子の種別
を識別可能としたことにより達成される。
An object of the present invention is to provide an improved structure of a semiconductor substrate that can automatically identify the types of multiple types of elements created on the same substrate even in such a case, and this purpose is achieved by the present invention. , a determination element is arranged on the surface of the semiconductor substrate together with at least one type of semiconductor element in accordance with the type of the semiconductor element, and the determination element is connected to a power terminal and a source provided on the surface of the semiconductor element. terminal,
and measurement pads are provided at positions corresponding to the arrangement positions of the plurality of output terminals, and measurement pads are provided at the same positions as the above-mentioned power supply terminals and source terminals for identification to identify the type of semiconductor element. An input terminal for supplying a signal and the remaining measurement pads are used as detection terminals, and the input terminals are connected through one of the detection terminals selected according to the type of semiconductor element. This is achieved by making it possible to identify the type of the corresponding semiconductor element from the position of the detection terminal where the identification signal is detected when the identification signal is applied to the input terminal.

以下本発明の一実施例を図面により説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例の半導体基板を示す
平面図で、2種類のマスクROMを形成した例を
示し、第2図は判定用素子のパターン構成の一例
を示す上面図、第3図は本実施例の試験手順を示
すフローチヤートである。
FIG. 1 is a plan view showing a semiconductor substrate according to an embodiment of the present invention, showing an example in which two types of mask ROM are formed, FIG. 2 is a top view showing an example of the pattern configuration of a determination element, and FIG. The figure is a flowchart showing the test procedure of this example.

本実施例では第1図に示すごとく半導体基板1
に第1のマスクROM素子2と第2のマスク
ROM素子3がそれぞれ区域,区域に配列さ
れた例を掲げて説明する。同図において41〜4
3は第1の素子2に対応する判定用素子4,51
〜58は第2の素子3に対応する判定用素子5で
ある。これら判定用素子4,5はそれぞれ1個ず
つとしてもよいが、矢印の方向に進行する試験の
進行方向に対し、各区域,の先頭位置に配設
することが必要である。
In this embodiment, as shown in FIG.
the first mask ROM element 2 and the second mask
An example in which the ROM elements 3 are arranged in areas will be explained. In the same figure, 41-4
3 is a determination element 4, 51 corresponding to the first element 2
-58 are the determination elements 5 corresponding to the second element 3. These determining elements 4 and 5 may be provided one each, but it is necessary to arrange them at the leading position of each area with respect to the direction in which the test progresses in the direction of the arrow.

この判定用素子としては例えば第2図に示すよ
うなものを用いることができる。同図a,bにお
いて6は第1、第2のマスクROM素子2,3の
第1の電源端子としてのVss(電源)端子、7は
第2の電源端子としてのVss(ソース)端子の配
設位置と同じ位置に設けられた入力端子、11,
12,13,…は同じくマスクROM素子2,3
の出力端子の配設位置と同じ位置に設けられた検
知端子で、いずれも測定用パツドである。マスク
ROMのような記憶装置はそのビツト数に対応す
る数、即ち8ビツト素子では8個の出力端子を有
する。本実施例では各判定用素子に前記8個の出
力端子の配設位置と同じ位置に検知端子11,1
2,13,…,およびVcc端子、Vss端子の配設
位置と同じ位置に入力端子6,7を設け、この2
つの入力端子6と7の間を、上記8個の検知端子
11,12,13,…のうちの1つを介して電気
的に接続した。この8つの検知端子11,12,
13,…のうちどの端子を接続するかは、素子の
種別に対応するよう定めればよい。第2図aは検
知端子11を、またbは検知端子12を介して接
続した例で、それぞれ素子2及び素子3に対応さ
せてある。
As this determination element, for example, one as shown in FIG. 2 can be used. In the figures a and b, 6 is the Vss (power supply) terminal as the first power supply terminal of the first and second mask ROM elements 2 and 3, and 7 is the arrangement of the Vss (source) terminal as the second power supply terminal. Input terminal provided at the same position as the installation position, 11,
12, 13,... are the same mask ROM elements 2, 3
The detection terminal is located at the same location as the output terminal, and both are measurement pads. mask
A storage device such as a ROM has a number of output terminals corresponding to its number of bits, ie, eight for an 8-bit device. In this embodiment, each determination element has detection terminals 11 and 1 at the same position as the eight output terminals.
2, 13, ..., and the input terminals 6 and 7 are provided at the same positions as the Vcc and Vss terminals.
The two input terminals 6 and 7 were electrically connected through one of the eight detection terminals 11, 12, 13, . . . . These eight detection terminals 11, 12,
Which terminal among 13, . . . should be connected may be determined in accordance with the type of element. FIG. 2A shows an example in which the detection terminal 11 is connected to the detection terminal 11, and FIG.

次に本実施例の試験の手順を第3図により説明
する。前述した如く被測定基板が移動台上に乗せ
られ、位置合わせが終了するとプローバーの測定
用探針がスタート位置の素子の各測定用パツドに
接触する。そして試験の開始に先立ちプログラム
に従つて先ずこの素子が判定用素子か否かを識別
する信号が前述の2つの入力端子6,7の間に送
出されると共に、8個の検知端子11,12,1
3……で信号の有無を検知する。
Next, the test procedure of this example will be explained with reference to FIG. As described above, the substrate to be measured is placed on the moving table, and when the alignment is completed, the measurement probe of the prober comes into contact with each measurement pad of the element at the starting position. Then, prior to the start of the test, according to the program, a signal identifying whether or not this element is a determination element is first sent between the two input terminals 6 and 7, and also sent to the eight detection terminals 11 and 12. ,1
3... detects the presence or absence of a signal.

本実施例では第1図に示した如く基板1のスタ
ート位置には第2図aの判定用素子4が配設され
ているので、8個の検知端子のうち11で信号が
検知される。従つてこの素子は判定用素子であつ
て、且つシヨートモードNo.1であることが認識さ
れる。すると、プログラムに従いシヨートモード
No.1に対応する試験プログラムが呼び出される。
次いでこのプログラムに従つて素子の試験が実行
される。このように一つのプログラムが選択され
ると、このあとに引き続く素子はこの選択された
プログラムに従つて試験が行なわれ、他のシヨー
トモードを有する判定用素子が検知されるまでプ
ログラムは変更されない。
In this embodiment, as shown in FIG. 1, the determining element 4 shown in FIG. 2a is arranged at the starting position of the substrate 1, so that signals are detected at 11 of the 8 detection terminals. Therefore, it is recognized that this element is a determination element and is in shot mode No. 1. Then, follow the program and switch to shoot mode.
The test program corresponding to No. 1 is called.
Next, the device is tested according to this program. When one program is selected in this manner, subsequent devices are tested according to the selected program, and the program is not changed until another determination device having a short mode is detected.

試験しようとしている素子が正規のROM素子
のときは、いずれの検知端子11,12,13,
……でも信号は検知されないので、この場合は判
定用素子ではないと判断され、上述の既に選択さ
れたプログラムに従つて直ちに試験が実行され良
否が判定される。
If the device to be tested is a regular ROM device, any detection terminal 11, 12, 13,
...However, since no signal is detected, in this case it is determined that it is not a determination element, and a test is immediately executed according to the already selected program described above to determine whether it is pass or fail.

試験が進行し区域のすべての素子の試験を終
了して区域に入ると、第2図bに示す判定用素
子が検知され、これはシヨートモードNo.2である
ことが認識されると直ちに試験プログラムはシヨ
ートモードNo.2に対するものと差し換えられ、区
域に対する試験が実行される。
When the test progresses and all the elements in the area have been tested and the area is entered, the judgment element shown in Figure 2b is detected, and as soon as it is recognized that this is shot mode No. 2, the test program starts. is replaced with that for shot mode No. 2 and the test for the area is performed.

なお、上述の試験プログラムは被試験試料の種
類に応じて作成し、シヨートモードによる対応付
けを行なつて主プログラムのサブルーチンとして
予め格納しておけばよい。
The above-mentioned test program may be created according to the type of sample to be tested, associated with the short mode, and stored in advance as a subroutine of the main program.

以上説明したごとく、同一基板上に複数種類の
素子を形成する場合でも、本発明に係る判定用素
子を各区域における試験の先頭位置に配設し、試
験の実行に当つては配設された判定用素子の種別
を検知して予め格納された試験用プログラムの中
から対応するものを選択使用することにより基板
試験を自動的に行なうことが可能となる。
As explained above, even when multiple types of elements are formed on the same substrate, the determination element according to the present invention is placed at the top position of the test in each area, and when the test is executed, By detecting the type of determination element and selecting and using a corresponding test program from pre-stored test programs, it is possible to automatically conduct a board test.

なお判定用素子の判別及びプログラムの選択は
ハードウエアにより行なうことも勿論可能である
が、前記一実施例において説明した如くプログラ
ム制御で行なう方が容易且つ実用的であろう。
Although it is of course possible to determine the determination element and select the program using hardware, it is easier and more practical to perform the determination using program control as described in the above embodiment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図は本発明の一実施例を示す図
で、それぞれ半導体基板を示す平面図、判定用素
子を示す平面図、第3図は上記一実施例を用いた
試験手順を示す工程図である。 図において、1は半導体基板、2及び3は半導
体素子、4及び5は判定用素子、6及び7は入力
端子、11,12,13,…は検知端子を示す。
FIG. 1 and FIG. 2 are diagrams showing an embodiment of the present invention, and FIG. 3 is a plan view showing a semiconductor substrate and a plan view showing a determination element, respectively, and FIG. 3 shows a test procedure using the above embodiment. It is a process diagram. In the figure, 1 is a semiconductor substrate, 2 and 3 are semiconductor elements, 4 and 5 are determination elements, 6 and 7 are input terminals, and 11, 12, 13, . . . are detection terminals.

Claims (1)

【特許請求の範囲】 1 少なくとも1種類の半導体素子と、該半導体
素子の種別に対応して形成された判定用素子を具
備し、 該判定用素子が、前記半導体素子表面に設けら
れた第1及び第2の電源端子、および複数個の出
力端子の配設位置と同じ位置にそれぞれ測定用パ
ツドを具え、 前記第1、第2の電源端子の配設位置に対応す
る測定用パツドを半導体素子の種別を識別するた
めの識別信号を供給する入力用端子、残りの測定
用パツドを検知端子とし、 前記入力用端子間を前記検知端子の中から半導
体素子の種別に対応して選択された1つを介して
接続しておき、 前記入力端子に識別信号を印加した時、該識別
信号が検出される検知端子の位置から、対応する
半導体素子の種別を識別可能とした判定用素子を
具備することを特徴とする半導体基板。
[Scope of Claims] 1. At least one type of semiconductor element, and a determination element formed corresponding to the type of the semiconductor element, wherein the determination element is a first type provided on the surface of the semiconductor element. and a second power terminal, and a measuring pad at the same position as the plurality of output terminals, and the measuring pad corresponding to the position of the first and second power terminals is connected to the semiconductor element. an input terminal that supplies an identification signal for identifying the type of the semiconductor element, the remaining measurement pads are used as detection terminals, and a terminal selected from among the detection terminals corresponding to the type of the semiconductor element is connected between the input terminals. and a determination element that is connected to the input terminal through the input terminal, and that when an identification signal is applied to the input terminal, the type of the corresponding semiconductor element can be identified from the position of the detection terminal where the identification signal is detected. A semiconductor substrate characterized by:
JP9943981A 1981-06-25 1981-06-25 Test method for semiconductor substrate Granted JPS582039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9943981A JPS582039A (en) 1981-06-25 1981-06-25 Test method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9943981A JPS582039A (en) 1981-06-25 1981-06-25 Test method for semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS582039A JPS582039A (en) 1983-01-07
JPS6329818B2 true JPS6329818B2 (en) 1988-06-15

Family

ID=14247437

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9943981A Granted JPS582039A (en) 1981-06-25 1981-06-25 Test method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS582039A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59115642U (en) * 1983-01-26 1984-08-04 日本電気アイシ−マイコンシステム株式会社 semiconductor wafer
JPS59139640A (en) * 1983-01-31 1984-08-10 Ando Electric Co Ltd Measuring device for integrated circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS567427A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor pellet
JPS5650526A (en) * 1979-10-02 1981-05-07 Mitsubishi Electric Corp Semiconductor device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS567427A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor pellet
JPS5650526A (en) * 1979-10-02 1981-05-07 Mitsubishi Electric Corp Semiconductor device

Also Published As

Publication number Publication date
JPS582039A (en) 1983-01-07

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