JPS6313341A - Semiconductor integrated circuit and test method thereof - Google Patents

Abstract

PURPOSE:To arrange quite freely a plural kinds of integrated circuits on a semiconductor wafer without being restricted at all and to permit it to test them individually and to simplify the control of manufacture of ICs by independently forming information which gives the kind of a test program within individual semiconductor chip regions. CONSTITUTION:Different kinds of integrated circuits are each formed within each chip region 1, 2 and 3 on a semiconductor wafer 10. Moreover, information to be served to selection of the test programs of the integrated circuits are formed in the interiors by an electric circuit and pads 11, 12 and 13, 21, 22 and 23 and 31, 32 and 33 for reading out the information from the respective electric circuits are formed within the respective chip regions. In the electric circuit to store test program selection information which is formed in each chip region, resistors R1-R6 are ready-arranged, and as the ratio of resistive division is made different according to types by selecting the positions of nodes 4, 5 and 6 according to the types, the combination of voltage values fitted to the kind of the kind of the test program of each type is coded and outputted to terminals 7, 8 and 9. Therefore, an IC testing device performs a decoding of the codes and according to the result, a test program can be selected.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit and a testing method thereof.

[Conventional technology]

In the manufacturing process of semiconductor integrated circuits, before cutting and separating a semiconductor integrated circuit substrate (hereinafter referred to as an IC wafer) into individual IC elements after completing the process of forming semiconductor integrated circuit elements (hereinafter referred to as IC elements), the IC wafer is All IC elements formed in the test are tested.

As is well known, in this jC wafer test, the IC wafer to be tested is placed on the moving table of the test equipment, and after accurate alignment, the test is placed on the pad provided on the surface of the IC element. The tip of the measurement probe that has been drawn out from the device is brought into contact with the device, and each test is performed according to a test program prepared in advance to determine the quality of the IC element. Next, by moving the moving table, the above operation is repeated for all IC elements, and all IC elements are tested.

All of the above operations are performed automatically, but when two or more types of IC elements are formed on the same wafer, the test program must be changed depending on the type of IC element, so it is necessary to change the test program depending on the type of IC element. The test cannot be performed automatically as described above. Such situations occur when relatively small orders are received, such as in the production process of mask ROMs that store information requested by users or gate arrays, or during the research and development stage of ICs.

[Problem that the invention seeks to solve]

Conventionally, an IC in which multiple types of IC elements are formed in this way
The method for automatic wafer testing is to arrange a certain number of each type of IC element on the IC wafer, and place a judgment element corresponding to each type at the beginning of the grouped area. Then, when the test device detects the determination element, it continues to be <IC.
A method of determining the type of element and selecting a test program corresponding to the determined type (for example, Japanese Patent Laid-Open No. 58-20
Publication No. 39), etc. have been proposed. However, according to this method, a certain number of IC elements of the same type must be formed in the same area on the IC wafer, which imposes restrictions on the arrangement of the IC elements on the IC wafer. In addition, if the judgment element is not formed correctly for some reason, and therefore the test equipment cannot judge this judgment element, all subsequent IC elements under test must correctly execute the test program. Unable to select
Furthermore, there was a drawback that correct tests were not conducted.

Another proposal is to associate the positional coordinates of each IC element formed on the IC wafer of the test sample with the type of test program to be executed for each IC element, and to use this correspondence information in advance in the test equipment. The position coordinates of the test execution element are memorized and sent from the movable stage to the test equipment in accordance with the movement of the mobile stage on which the IC wafer of the test sample is placed, and the test equipment collates these position coordinates with the corresponding information. There was a way to select a test program. However, even with this method, there is a process that involves aligning the origin of the coordinates on the IC wafer between the process for forming IC elements on the substrate (mainly the process for forming IC elements on the substrate) and the IC wafer testing equipment. In the case where the arrangement method of IC elements is different for each IC wafer, the above-mentioned correspondence information must be added to each IC wafer, which has the disadvantage that management in the manufacturing process becomes extremely complicated.

[Means for solving problems]

In the semiconductor integrated circuit of the invention of water bottle 1, information for selecting a test program used for testing the integrated circuit is formed in a part of the semiconductor chip on which the integrated circuit is formed as an electric circuit, and is connected to the electric circuit. It is configured with a pad for reading information.

The semiconductor integrated circuit of the invention of Water Bottle 2 is a semiconductor wafer in which one type of integrated circuit is formed in one chip area, and a plurality of types of integrated circuits are formed in one wafer. Information for selecting a test program to be used for testing the integrated circuit is formed in a part of each chip area by an electric circuit, and the information is read out for each chip area to select a test program to test the integrated circuit. It is used to test circuits.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a layout diagram of an embodiment of a semiconductor integrated circuit according to the present invention.

On the semiconductor wafer 10, a large number of chip areas are arranged vertically and horizontally in which one type of integrated circuit is formed within one chip area. Figure 1 shows three chip areas 1
, 2.3 is shown.

Different types of integrated circuits are formed in each of the chip areas 1, 2.3. In addition, the information used to select the test program for integrated circuits is formed internally using electric circuits.
Pads (1
1,12,13), (21,22,23), (31,3
2, 33> are formed within each chip area. The electric circuit will be described later. Pads other than the above pads are terminals derived from electrical circuits formed according to the functional purpose of each IC element, and are contacted with the probe of the test equipment to send and receive signals for electrical testing. This is the terminal to perform. For these pads, chip area 1.2.3
Even if the types of integrated circuits are different, the same probe is placed at the same position on each IC element because the same probe is tested by contacting elements 1 → 2 → 3 in order. .

These pads generally serve as element-side connection terminals for connection with external lead terminals when external lead terminals are attached after each IC element is separated into individual IC elements in a later process of IC manufacturing.

FIG. 2 is a circuit diagram showing an example of an electric circuit formed in each chip area of FIG. 1 and storing test program selection information.

By arranging the resistors R1 to R6 and selecting the positions of nodes 4 and 5゜6 according to the product, the resistance division ratio will differ depending on the product. A combination of voltage values depending on the type is encoded and output. Before testing each IC element, the IC testing apparatus measures the voltages of these test program determination pads, decodes the codes, and can select a test program in accordance with the results.

〔Effect of the invention〕

As explained above, in the present invention, since the information giving the type of test program is formed independently in each semiconductor chip area, integrated circuits with multiple pillars can be formed on a semiconductor wafer completely freely without any restrictions. In extreme cases, even if all adjacent integrated circuits are of different types, it is possible to test them individually. In addition, even if the test program judgment circuit is not formed correctly for some reason during the integrated circuit formation process, the defect is caused by the IC.
Since it is limited to only one element and does not cause further damage, and because the identification name of the test program itself can also be set as the output from the judgment circuit, it is possible to create a correspondence table that corresponds to the type of test program during processing. is unnecessary and does not use coordinate information on the semiconductor wafer.
There is no need to prepare in advance a correspondence table between the position coordinates of each IC element and the test program that connects the IC element forming process and the IC wafer testing process, which simplifies the management of IC manufacturing. The effect of this can be obtained.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of an embodiment of the semiconductor integrated circuit of the present invention, and FIG. 2 is a circuit diagram of an example of an electric circuit that stores test program selection information formed in each chip area of FIG. 1. . 1.2.3...Chip area, 4,5.6...Node,
7.8.9... Pad, 10... Semiconductor wafer,
11.12,13,21,22,23,31.3233
...Pad, R1-R6...Resistance.

Claims (2)

[Claims] (1) Information for selecting a test program used for testing the integrated circuit is formed in a part of the semiconductor chip area where an integrated circuit is formed, and a circuit is connected to the electric circuit to read out the information. A semiconductor integrated circuit characterized by being provided with a pad. (2) One chip area has one type of integrated circuit formed in the chip area, and multiple types of integrated circuits are formed in one wafer for each chip area of the semiconductor wafer. Information for selecting a test program used for testing the integrated circuit is formed in part by an electric circuit, and the integrated circuit is tested by reading out the information for each chip area and selecting a test program. A test method for semiconductor integrated circuits.