KR19980026610A - Electrical test method for wafers with chips with complex functions - Google Patents

Abstract

The present invention relates to a method of electrically testing a wafer having a multifunction chip such as digital-analog or logic-digital with a probe of a probe station. Loading the wafer into a primary test apparatus for testing; (b) electrically primary testing the chips formed on the wafer loaded into the primary test apparatus; (c) marking an ink on an upper surface of the chip, which is determined to be defective in the first test of the chips; (d) loading the wafer on which the primary test is completed into a secondary test apparatus; (e) image processing the wafer loaded in the secondary test apparatus to determine the position of the ink-marked chip that has received a bad chip determination; (f) issuing a command to skip the secondary test by sending position information of the chip determined by the ink mark to the secondary test device; (g) electrically performing a second test except for a chip that has received the test skip command; (h) marking ink on the upper surface of the chip determined as defective by the secondary test result; The present invention relates to providing an advantage of increasing productivity by using a test method of a wafer having a chip having a composite function formed thereon comprising a.

Description

Electrical test method for wafers with chips with complex functions

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrical test method of a wafer in which a semiconductor circuit process is completed, and more particularly, to a test method in a probe device for electrically testing a wafer having a complex structure.

Electrical die sorting (EDS) is performed to select chips of good and defective products after the process of designing a semiconductor product and fabricating the product on a wafer is completed.

In order to test a wafer on which a plurality of chips are formed, a prober station including a function of loading the wafer sequentially and moving the wafer sequentially by the interval of the chips is needed. There are two main functions.

The first function is to index and move the position of the wafer so that all the chips in the wafer can be tested. The other is to conduct an electrical test with a probe, and then if it is a bad chip, It is a function to mark ink on the upper surface.

In this way, the chip marked with ink is judged to be defective and does not proceed with the next package process.

Recently produced chips are a combination of memory and analog at the same time, chips with a combination of memory and logic, and a combination of logic and analog to meet the needs of the buyer. .

However, these complex chips must test each function separately, and a single test device cannot test each function.

1 is a flow chart showing a method of testing a wafer having a composite chip according to the prior art, and FIG. 4 is a schematic diagram showing a prober station.

First, referring to FIG. 4 and FIG. 1, the wafer 10 is fixed by the lower fixing die 20 to be loaded into the prober station, which is the primary test apparatus, and to be tested 101 for electrical testing. The primary test 102 is performed by referring to a test pad (not shown) of the chip 12 in which the probe 30 fixed to 40 is formed in each region of the wafer 10. .

In addition, the first test result 103 of the chips on the wafer 10 that are determined to be defective is performed with an ink marking 15 on the upper surface, and the good chips do not display the secondary test. The device is loaded 108. The first test device and the second test device are for testing each function of the combined chip, and which function is to be prioritized can be arranged according to the efficiency of the test.

The wafer 10 loaded in the secondary test apparatus 108 sequentially performs the secondary test 109 according to a test procedure program, and the secondary test results 110 on the wafer 10. If it is determined that the chip is defective, the ink mark 15 is applied to the upper surface of the chip 12.

As described above, according to the related art, the wafer 10 includes a method of testing a chip having a complex function through the primary test device and the secondary test device.

The problem with this test method is that the second test is performed on all the chips on the wafer, regardless of the state where the first test is performed and the ink is marked on the chip that is determined to be defective. Is that there is.

That is, there is a disadvantage in that the chips that are determined to be defective in the first test are sequentially tested in the second test and the chips that are already determined to be repeatedly tested are repeatedly tested. This leads to an increase in test cost and a decrease in productivity.

Accordingly, an object of the present invention is to provide a test method for a wafer having a chip having a composite function formed thereon, in order to overcome the above-mentioned disadvantages, thereby shortening the product test time and improving productivity and cost.

1 is a flowchart illustrating a method of testing a wafer having a composite chip according to the prior art;

2 is a flowchart illustrating a method of testing a wafer having a composite chip according to the present invention;

3 is a flow chart showing another method of testing a wafer having a composite chip according to the present invention;

Figure 4 is a schematic diagram showing a wafer probe station and an image sensor, which is an electrical test apparatus for a typical wafer.

Description of the main symbols in the drawings

10: wafer 12: chip

15 ink marking 20 lower fixing die

30: probe 40: test head

50: image sensor

In order to achieve the above object, the present invention includes the steps of (a) loading the wafer in the primary test apparatus for testing chips having a complex function formed on the wafer; (b) electrically primary testing the chips formed on the wafer loaded into the primary test apparatus; (c) marking ink on an upper surface of the chip, which is determined to be defective among the chips as a result of the first test of the chips; (d) loading the wafer on which the primary test is completed into a secondary test apparatus; (e) image processing the wafer loaded in the secondary test apparatus to determine the position of the ink-marked chip that has received a bad chip determination; (f) issuing a command to send the position information of the chip determined by the ink mark to the secondary test apparatus and skip the chip determined by the ink mark in the secondary test; (g) electrically performing a second test on the remaining chips except for the chips that have received the test skip command; (h) marking ink on the upper surface of the chip determined as defective by the secondary test result; It provides a test method of a wafer having a chip having a complex function, characterized in that it comprises a.

In addition, another method for achieving the above object is (a) loading the wafer into the primary test apparatus for testing chips having complex functions formed on the wafer; (b) electrically primary testing the chips formed on the wafer loaded into the primary test apparatus; (c) marking ink on an upper surface of the chip, which is determined to be defective among the chips as a result of the first test of the chips; (d) image processing the wafer to determine the positions of the ink-marked chips and to transmit the determined position information to a control device storing the determined position information; (e) loading the chip on which the first test is completed into a second test device; (f) transferring information stored in the control device to a secondary test device to skip a test of the ink-marked chip and perform a secondary test; And (g) marking ink on the upper surface of the chip determined as a result of the secondary test failure; It provides a test method of a wafer having a chip having a complex function, characterized in that it comprises a.

Hereinafter, with reference to the drawings will be described in more detail the present invention.

2 is a flowchart illustrating a method of testing a wafer having a composite chip according to the present invention, FIG. 3 is a flowchart illustrating another method of testing a wafer having a composite chip according to the present invention, and FIG. 4 is an electrical test apparatus of a general wafer. A schematic diagram showing an in-wafer probe station and an image sensor.

First, referring to FIGS. 2 and 4, the wafer is placed on the prober lower fixed die 30 of the primary test apparatus to test the chips 12 having the complex functions formed on the wafer 10. Load 101 (10). That is, a probe 30 mounted on a lower surface of the test head 40 to perform the electrical test may move to sequentially test the chips 12 formed on the wafer 10. It is to be fixed on the lower stationary die 20 of the bur station.

Then, the first test device 102 is electrically contacted with the probes 30 and the chips 12 formed on the wafer 10 loaded in the primary test apparatus 101, and the primary test 102 is performed. The test 102 may first select and use a suitable efficiency in a test process such as an analog test, a memory test, or a logic test.

The chips 12 which are determined to be defective in the primary test result 103 are subjected to the primary ink marking process 106 so that the defects can be identified by making an ink mark 15 on the upper surface thereof, and the ink marking process 106 is performed. ) Is performed through an ink dotting apparatus.

In addition, the chips that are determined to be good in the primary test result 103 do not perform the ink marking 15, so that the primary test 102 of the wafer 10 is completed.

In addition, the wafer 10 on which the primary test 103 is completed is loaded 108 into the secondary test apparatus, and the method and principle of loading 108 into the secondary test apparatus are loaded into the primary test apparatus. Proceeds in the same manner as in 101.

Then, the wafer 10 loaded in the secondary test apparatus 108 is image processed using an image scanner 50, and the image scanner 50 is processed. The position information of the chip of the primary ink mark 106 is found, and the image processing 200 is performed to obtain the position information of the chip of the primary ink mark 106 on the wafer 10. Transfer to the control unit of the test device. The information transmitted from the image processing 200 transmits a command to test skip the position of the chip marked with the primary ink 106 so that the second test 109 does not proceed with the electrical test and then proceeds. Test the chips sequentially.

That is, the position of the chip which is found to be defective on the wafer 10 is detected by the image sensor, and the position is sent to the secondary test control device so that the test of the defective chip is not retested.

In addition, the second test result 111 is performed on the upper surface of the chip determined as defective by the second test result using the ink dotting apparatus to display the defective product.

Referring to FIG. 3, as another example according to the present invention, the wafer 10 is loaded 101 into the primary test apparatus for testing chips 12 having complex functions formed on the wafer 10. , Which is the same as described with reference to FIG. 2.

The first test 102 is electrically performed by using a probe on the chips 12 formed on the wafer 10 loaded in the first test apparatus 101, and the first tests of the chips 12 are performed. Result 103 The primary ink display 106 is applied to the upper surface of the chip determined as defective among the chips 12.

The wafer 10 is then subjected to image processing with an image sensor to transfer the position information of the primary ink mark 106 to the control device 210, and the wafer is loaded 108 into the secondary test device.

The position information of the primary ink marks 106 stored in the control device 210 is converted into a secondary test skip command 207 and transmitted to the secondary test apparatus, and the secondary test of the wafer 10 is performed. The second test 109 is performed on the chips at positions other than the skip command 207.

The chip determined as defective in the secondary test result 110 is subjected to the secondary ink markings 111 in the same manner as the primary test result 103, and then the entire test process is completed. The first test 103 and the second test 109 may be used by a technician performing a test to determine an order of an analog test or a memory test according to test efficiency.

Therefore, the test method according to the present invention overcomes the disadvantages of performing the double test in which the chip, which has already been determined to be defective in the first test, is also tested in the second test. The advantages of increasing productivity by providing a simple image scanner and image processing device at the station.

Claims (4)

(a) loading the wafer into a primary test apparatus for testing chips having complex functions formed on the wafer; (b) electrically primary testing the chips formed on the wafer loaded into the primary test apparatus; (c) marking the chips on an upper surface of the chip, which is determined to be defective among the chips as a result of the first test; (d) loading the wafer on which the primary test is completed into a secondary test apparatus; (e) image processing the wafer loaded in the secondary test apparatus to determine the position of the ink-marked chip that has received a bad chip determination; (f) issuing a command to send the position information of the chip determined by the ink mark to the secondary test apparatus and skip the chip determined by the ink mark in the secondary test; (g) electrically performing a second test on the remaining chips except for the chips that have received the test skip command; (h) marking ink on the upper surface of the chip determined as defective by the secondary test result; Test method of a wafer having a chip having a complex function formed, comprising a. 10. The method of claim 1, wherein the first testing step is in electrical contact with the probe in direct contact with the probe. The complex function of claim 1, wherein image processing is performed on the positions of the first ink marked chips using an image sensor capable of recognizing the wafer loaded into the secondary test apparatus as image information. Method for testing wafers with formatted chips. (a) loading the wafer into a primary test apparatus for testing chips having complex functions formed on the wafer; (b) electrically primary testing the chips formed on the wafer loaded into the primary test apparatus; (c) marking the chips on an upper surface of the chip, which is determined to be defective among the chips as a result of the first test; (d) image processing the wafer to determine the positions of the ink-marked chips and transmitting the information to a control device that stores the position information of the identified chips; (e) loading the chip on which the first test is completed into a second test device; (f) transferring information stored in the control device to a secondary test device to skip a test of the ink-marked chip and perform a secondary test; (g) marking ink on an upper surface of the chip determined as a result of the secondary test failure; Test method of a wafer having a chip having a complex function formed, comprising a.