JPS63296245A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent stepped cuttings, wedged cuttings and the like from being generated in an upper wiring layer, by forming an Si oxide layer, which contains As in a specific ratio or above, on a wiring layer and next forming openings in this oxide layer and heating them in an atmosphere of an inactive gas. CONSTITUTION:A thick oxidizing film 3 is formed selectively on a semiconductor substrate 1. Next an oxidizing film 4 serving as a gate oxidation film is formed on each part which is not covered with the film 3. Further a first wiring layer 5 is formed selectively thereon. In succession the whole surface including this layer 5 is coated with an Si oxide layer 6 containing As of 2.7 atom% or more. After openings 9s, 9d, 10s, 10d are formed on this layer 6, heat treatment in an atmosphere of an inactive gas is performed to provide them with fluidization processing. Edge parts of respective windows 9s, 9d, 10s, 10d in the layer 6 are thus rounded to have smooth shoulder parts by the fluidization processing. Next a second wiring layer 11 is formed on this layer 6. Accordingly, stepped cuttings and wedged cuttings and the like can be prevented from being generated in a layer 11 and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device suitable for use in, for example, semiconductor integrated circuit devices.

In semiconductor integrated circuits, there is a demand for higher density, and along with this, there is a demand for wiring on a semiconductor substrate to be layered, to be finer, and to have higher density. In this case, if there are steep irregularities on the surface to which these wirings are attached, problems such as so-called breakage or wedge breakage of the wiring layer, and breakdown voltage between the wirings occur due to the irregularities. Therefore, it is desirable that the surface on which the multilayer wiring layer is formed has as many irregularities as possible.

Various methods have been proposed for smoothing the unevenness of the surface to which the wiring layer is adhered.

For example, a silicon oxide layer doped with phosphorus (P), a so-called phosphorus-doped glass layer, is placed, heated and fluidized to create a smooth, rounded surface, and the upper l- wiring layer is formed on top of this. A method is proposed. However, in this case, the phosphorus-doped silicon oxide layer has a relatively high melting point, and a high temperature of about 1100°C is required to fluidize it and smooth out its unevenness. Sources of each region as a circuit element of an integrated circuit, such as an insulated gate field effect transistor element (hereinafter referred to as a MOS transistor).

This method has the disadvantage that impurities in each drain region or diffusion wiring are diffused, making it difficult to miniaturize the pattern of these regions.Also, this phosphorus-doped silicon oxide has disadvantages such as low hygroscopicity.

The present invention provides a method for manufacturing a semiconductor device that is free from such drawbacks and can effectively avoid disconnection, wedge breakage, etc. in the wiring layer and can provide a highly reliable semiconductor device.

An example of the manufacturing method of the present invention will be explained with reference to FIGS. 1 to 1. In the illustrated example, two MO3I transistors are formed on a common semiconductor substrate +1).

In this case, first, as shown in FIG. 1, for example, an N-type silicon semiconductor substrate +1) is provided, and facing its − principal surface (la), a P-type region (2) is selectively formed using a well-known technique, for example. It is formed by an ion implantation method, a diffusion method, or the like. Then, facing this main surface (la), N-channel type and P-channel type MOS) transistors are formed in the P-type w4 region (2) and in the area other than this region (2), respectively. , a thick acid 4tA layer 3) is formed by thermal oxidation on the main surface (la) at the portions other than the portions where each MOS transistor is to be formed. Although not shown, the thick 5i02 oxide film (3) is formed by selectively depositing and patterning an oxidation-resistant mask layer, such as a Si3N4 layer, on the main surface (1a), and using this as a mask, thermal oxidation treatment is performed. Then, a thick oxide film (3
).

Next, as shown in FIG. 2, a thin layer of, for example, 5T (h oxide lit (4)), which will become the gate a film, is formed by thermal oxidation on each part not covered by the thick oxide 15ij (31). A first wiring 1415) is selectively formed thereon, and using this as a mask, a P-type source region (7s) and drain region (7d) and an N-type source region (8s) and drain region are formed using a well-known technique. (8d) In the illustrated example, this first wiring layer (5) consists of a portion that will eventually become the gate electrode of the MO5I-transistor and a wiring portion extending from this, although not shown. The wiring portion (5) may be composed of a polycrystalline silicon layer or a silicide layer such as PT which is heavily doped with impurities and has a low specific resistance.

The gate electrode (5) made of this polycrystalline silicon layer is formed by forming a polycrystalline silicon layer on the entire surface by a well-known technique such as chemical vapor deposition (CVD), and then patterning by photoetching, for example. Next, the entire surface including the first wiring layer (5) is coated with arsenic (As).
A layer (6) of silicon oxide or arsenic doped glass containing at least 2.7 atomic percent of arsenic is deposited. This silicon oxide layer (61) containing arsenic A3 is formed by feeding each gas of ^5cffi3+5IH4+ 02 into a heating furnace in which the base body +11 is placed, using N2 gas as a carrier gas, and causing a thermal decomposition reaction to form the base body +1). It can be formed on top by chemical vapor deposition. In this case, A in 屓(6)
The sweetness of S can be selected by controlling the supply phase of ^5c13.

Next, as shown in FIG. 3, As doped oxide silicon 1
iit (61 and 5i below this (h oxidizing liquid 1fi (
4), especially the area (7s) (7d) (8s
) (8d) Each electrode window or opening (9s) on top
(9d) (10s) (10d) is drilled. In this case, these windows (openings) (9!l) (9
d) (10g) The edge of (10d) forms a steep step.

Next, the oxide silicon layer is heated to a temperature of 800°C or higher, for example, 80°C.
Heat treatment is performed at 50°C for 10 minutes to fluidize this. By doing this, silicon oxide Jd (
6) Each window (9s) (9d) (10s)
The edge at (10d) becomes fourth due to its fluidization.
As shown in the figure, it forms a rounded and gentle body. In this case, the As-doped oxide layer (6) is fluidized at a relatively low temperature of about 800°C or higher, and heating for fluidization at such a low temperature, for example, about 850°C, may damage other regions. This heat treatment for fluidization is particularly carried out in an inert gas such as N2.

Next, as shown in Figure 5, these windows (9s) (9d
) (10g) (10d) A metal layer such as aluminum Affi is deposited on the entire surface by vapor deposition or the like, and this is patterned by, for example, photoetching to form a pattern in each region (7s) (7d) (8s).
A second wiring layer (11) is formed on (8d), which serves as an ohmically attached electrode and constitutes a wiring section.

Next, as shown in FIG. 6, an insulating layer (12) such as S+02 is formed over the entire surface of the second wiring layer (11) by chemical vapor deposition (CVD).

Next, as shown in FIG. 7, windows (12a) are formed in required portions of the insulating layer (12) by, for example, photoetching.
2 (2) in the intended figure, through which the third wiring layer (13) is formed by, for example, heating the entire surface of aluminum and patterning it by photo-etching.
A semiconductor integrated circuit in which a MOS transistor is formed is obtained.

As mentioned above, in the present invention, As is particularly used as an impurity.
A silicon oxide layer (6) doped with is used, and when the impurity concentration is 2.5 at% or more, particularly 2.7 at% or more, fluidization by heating in an indestructible gas is possible. Will it become possible and will it become heated again in history? , 1 degree can be fluidized at temperatures as low as 800°C or higher, and as a result, as explained in Fig. 4, the periphery of the step formed by the opening of the electrode window becomes rounded and smooth. Since the second wiring layer (11) made of, for example, aluminum is formed on the second wiring layer (11) made of aluminum, there will be no breaks or wedges, so it can be formed into a fine pattern. Accordingly, it becomes easy to increase the density of wiring patterns, and a highly reliable semiconductor integrated circuit can be obtained.

As described above, according to the present invention, heat treatment for fluidizing silicon oxide containing As can be performed in an inert gas, but by performing this heating in an inert gas, For example, to eliminate the inconvenience of forming an oxide film on the opening when the process is carried out in an oxidizing atmosphere, and therefore eliminate the need for a step of removing the oxide film from the opening after fluidization treatment, thereby simplifying the number of manufacturing steps. Can be done.

Further, as mentioned above, in the present invention, silicon oxide jiii +61 containing arsenic As is used, but in this case, 2.5 atomic percent of As is ^s20]
This corresponds to 4 mol% or more. In addition, when this silicon oxide layer (6) is directly formed on a silicon nordium or polycrystalline silicon layer, that is, the first wiring layer (5), etc., the above-mentioned heat treatment for fluidization is performed using N2, etc. When carrying out the process in an inert gas, if there is a risk of surface roughness, etc.
It is desirable to form the silicon oxide layer (6) through a SiO2 oxide film as thin as 0.000. By doing so, the occurrence of the above-mentioned surface roughness etc. can be avoided.

Further, in the present invention, an As-doped silicon oxide layer (6) is used, but if it is formed, this m(61
It is also possible to include a large amount of As in the substrate and use this as an impurity to form the diffusion region of the substrate (1). Fluidization is performed during this diffusion heat treatment.

[Brief explanation of the drawing]

FIGS. 1 to 7 are enlarged cross-sectional views of each process other than an example of the manufacturing method of the present invention. (1) is a semiconductor substrate, (2) is a region formed in a part of a different conductivity type, (3) is a thick oxide film, (4) is a dielectric breakdown film, and (5) is a first wiring l. -1 (6) is a silicon oxide layer containing arsenic, and (11) is the wiring layer shown in FIG. Figure 1

Claims (1)

[Claims] A first
a step of forming a silicon oxide layer containing 2.7 atomic % or more of As on the first wiring layer; and a step of forming a silicon oxide layer containing 2.7 at. A semiconductor device comprising the steps of forming an opening, fluidizing the silicon oxide layer by heating it in an inert gas, and forming a second wiring layer on the silicon oxide layer. Manufacturing method.