JPS63295981A - Electrostatic breakage tester for semiconductor device - Google Patents

Electrostatic breakage tester for semiconductor device

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Publication number
JPS63295981A
JPS63295981A JP62132229A JP13222987A JPS63295981A JP S63295981 A JPS63295981 A JP S63295981A JP 62132229 A JP62132229 A JP 62132229A JP 13222987 A JP13222987 A JP 13222987A JP S63295981 A JPS63295981 A JP S63295981A
Authority
JP
Japan
Prior art keywords
current
voltage
current value
electrostatic pulse
application
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62132229A
Other languages
Japanese (ja)
Other versions
JPH067154B2 (en
Inventor
Minoru Nozoe
野添 実
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP62132229A priority Critical patent/JPH067154B2/en
Publication of JPS63295981A publication Critical patent/JPS63295981A/en
Publication of JPH067154B2 publication Critical patent/JPH067154B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable a breakage judgment to be performed with a high accuracy by comparing a current value after the application of an electrostatic pulse and an initial current value with each other in a leakage current region and in a large current region. CONSTITUTION:A voltage value set in advance is applied to the pin P1 of an IC 10 to be tested via a current supply/current measuring circuit 5 from a personal computer 2. After measured by the circuit 5, a flowing current is A/D-converted 6 and set voltage-current values are stored in the personal computer 2 as initial characteristics. Then, after an electrostatic pulse is applied to the pin P1 from an electrostatic pulse generating circuit 9, a current value for the application of the set voltage is measured and voltage-current characteristics after the application of the electrostatic pulse are stored into the memory of the personal computer 2. Those processings are sequentially conducted on the pins. The stored characteristic values of the pins are classified to a leakage current region and a large current region. In the leakage current region, whether the current value after the application of the electrostatic pulse is increased from an initial current value up to a reference current value or above and, in the large current region, whether the current value after the application of the electrostatic pulse is changed at above a prescribed rate are judged and the pin whose current value exceeds a reference value is judged as a defective pin.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 この発明は、IC,LSI等の良否判定に使用する半導
体装置の静電破壊試験装置に関する。
DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application This invention relates to an electrostatic breakdown testing device for semiconductor devices used for determining the quality of ICs, LSIs, and the like.

(ロ)従来の技術 従来、ICやLSI等の静電破壊強度を測定するのに、
第3図に示す測定回路を使用している。
(b) Conventional technology Conventionally, to measure the electrostatic breakdown strength of ICs, LSIs, etc.
The measurement circuit shown in FIG. 3 is used.

同図において測定器として静電パルス印加器11とカー
ブトレーサ12を使用している。静電パルス印加器11
とカーブトレーサ12と被供試験■C13の各GND端
子が共通接続される一方、静・電パルス印加器11の子
端子とカーブトレーサ12の子端子がスイッチSの切替
えにより、選択的に被供試ICl3の試験端子(ピン)
P、に接続さ−れKいる。この測定回路において、先ず
スイッチ”Sをカーブトレー1月2に投入し、静電パル
ス印加前のV−I(電圧−電流)特性を初期特性として
目視で測定し覚えておく、次にスイッチSを静電パルス
印加器11側に投入し、端子P+にパルスを印加する。
In the figure, an electrostatic pulse applicator 11 and a curve tracer 12 are used as measuring instruments. Electrostatic pulse applicator 11
The GND terminals of the curve tracer 12 and the test object C13 are commonly connected, while the child terminals of the electrostatic/electric pulse applicator 11 and the child terminals of the curve tracer 12 are selectively connected by switching the switch S. Test terminal (pin) of test ICl3
P is connected to K. In this measurement circuit, first put the switch "S" into the curved tray, visually measure and memorize the V-I (voltage-current) characteristics before applying the electrostatic pulse as the initial characteristics, then switch "S" is applied to the electrostatic pulse applicator 11 side, and a pulse is applied to the terminal P+.

そして、再びスイッチSをカーブトレーサ12側とし、
V−1特性を得、覚えている初期特性と、今回のパルス
印加後の特性を比較し、破壊を判定する。この場合、判
定をレンジa、b、cに亘って初期特性と目視で比較す
る。
Then, set the switch S to the curve tracer 12 side again,
The V-1 characteristic is obtained and the memorized initial characteristic is compared with the characteristic after the current pulse application to determine destruction. In this case, the determination is visually compared with the initial characteristics over ranges a, b, and c.

被供試ICl3の全ての端子の破壊電圧を出す場合には
、スイッチSをカーブトレーサ12に投入しておき、試
験端子を順次切替えて、レンジa、b、cに亘り、各端
子の初期特性を覚えておき、次にスイッチSを静電パル
ス印加器11に投入し、一方、試験端子を順次切替えし
、各試験端子にパルスを印加する。その後、再びスイッ
チSをカーブトレーサ12に投入し、試験端子を順次切
替えて、各端子のV−1特性を得、レンジa、b、cに
亘り、初期特性と目視で比較する。
In order to obtain the breakdown voltage of all terminals of the ICl3 under test, switch S is turned on to the curve tracer 12, and the test terminals are sequentially switched over ranges a, b, and c, and the initial characteristics of each terminal are determined. Next, switch S is turned on to the electrostatic pulse applicator 11, while the test terminals are sequentially switched and a pulse is applied to each test terminal. Thereafter, the switch S is again turned on to the curve tracer 12, the test terminals are sequentially switched, the V-1 characteristics of each terminal are obtained, and the results are visually compared with the initial characteristics over ranges a, b, and c.

静電破壊を判断するのに、上記した目視比較の他に、静
電パルス印加前のV−I特性に対し、パルス印加後の変
動を百分率で計算して、尾的に判定する方法がある。こ
の方法はICの各端子間の電圧−電流時性には、第4図
(a)(b)に示すものがあることに着目し、alのリ
ーク電流部、a2の順方向電流部、a3のブレークダウ
ン領域について、それぞれ電流値比較を行い変動度合い
を百分率で表わし、所定%以上を不良と判定するもので
ある。
In addition to the above-mentioned visual comparison, there is a method of determining electrostatic damage by calculating the percentage change in the V-I characteristics after the electrostatic pulse is applied to the V-I characteristics before the electrostatic pulse is applied. . This method focuses on the fact that the voltage-current characteristics between each terminal of an IC are as shown in FIGS. 4(a) and 4(b). For each breakdown region, current values are compared and the degree of variation is expressed as a percentage, and a predetermined percentage or more is determined to be defective.

(ハ)発明が解決しようとする問題点 上記した静電パルス印加器とカーブトレーサを用いて目
視で破壊を判定する技術は、Vi特性の初期特性を覚え
ておくことは、人間の眼で全レンジに亘り行なうことは
不可能に近い。写真撮影装置を使用して、初期特性を記
録することは可能であるが、これをICの全端子、全レ
ンジに亘り行おうとすれば、やはり作業効率上不可能で
ある。
(c) Problems to be Solved by the Invention The technique of visually determining destruction using the electrostatic pulse applicator and curve tracer described above requires that the human eye remember the initial characteristics of Vi. It is almost impossible to do this over a range. Although it is possible to record the initial characteristics using a photographic device, it is still impossible to do so over all terminals and all ranges of the IC in terms of work efficiency.

また、目視比較では、微妙な特性の変動や測定基準の変
動量が定量的な値として出ていないため、高精度な判定
が期待できず、誤判定のおそれが多いと言う問題点があ
る。
In addition, visual comparison does not provide quantitative values for subtle variations in characteristics or variations in measurement standards, so there is a problem in that highly accurate judgments cannot be expected and there is a high risk of erroneous judgments.

一方、百分率比較による判定は、一応定量的な判定は可
能であるが、それでもリーク電流領域は、初期電流値が
101A程度と、順方向電流領域と比し、3桁程低いた
め、初期電流値の読取り誤差が大きく、例え自動試験器
で読取るにせよ、精度の良い破壊判定は困難である。
On the other hand, although it is possible to make a quantitative determination based on percentage comparison, the initial current value in the leakage current region is still around 101A, which is about three orders of magnitude lower than the forward current region. The reading error is large, and even when reading with an automatic tester, it is difficult to accurately determine failure.

この発明は、上記に鑑み、定量的に判定でき、しかも高
精度な判定が可能な半導体装置の静電破壊試験装置を提
供することを目的としている。
In view of the above, it is an object of the present invention to provide an electrostatic breakdown testing device for semiconductor devices that is capable of making quantitative and highly accurate decisions.

(ニ)問題点を解決するための手段 この発明の半導体装置の静電破壊試験装置は、予め特性
測定用の電圧及び静電パルス発生用の電圧を設定する電
圧設定手段と、この電圧設定手段で設定される電圧を被
供試半導体装置の所定端子と共通基準電位端子間に印加
し、対応して流れる電流値を取込む電圧供給/電流測定
手段と、前記静電パルス発生用の電圧に応じた静電パル
スを発生し、前記特性測定用の電圧に代えて、前記被供
試半導体装置の所定端子に印加する静電パルス発生手段
と、この静電パルスの印加前と印加後における前記特性
測定用の電圧と電圧供給/電流測定手段により取込まれ
る電流値との関係をそれぞれ初期特性及び静電パルス印
加後の特性として記憶する特性記憶手段と、この特性記
憶手段に記憶される特性の電流値をリーク電流領域とリ
ーク電流領域以上の大電流領域とに分類する電流領域分
類手段と、このリーク電流領域では、静電パルス印加後
の電流値が初期電流値より所定の基準値以上大である場
合に、その端子を不良端子と判定する第1の不良判定手
段と、大電流領域では静電パルス印加後の電流値が初期
電流値に対し、所定割合以上変動した場合に、その端子
を不良端子と判定する第2の不良判定手段とから構成さ
れている。
(d) Means for Solving the Problems The electrostatic breakdown testing apparatus for semiconductor devices of the present invention includes a voltage setting means for setting in advance a voltage for measuring characteristics and a voltage for generating electrostatic pulses, and this voltage setting means. a voltage supply/current measuring means that applies a voltage set by the voltage between a predetermined terminal of the semiconductor device under test and a common reference potential terminal and obtains a corresponding current value; an electrostatic pulse generating means for generating an electrostatic pulse according to the characteristic measurement and applying it to a predetermined terminal of the semiconductor device under test in place of the voltage for measuring the characteristics; A characteristic storage means for storing the relationship between the voltage for characteristic measurement and the current value taken in by the voltage supply/current measurement means as an initial characteristic and a characteristic after application of an electrostatic pulse, respectively; and a characteristic stored in the characteristic storage means. current region classification means for classifying the current value into a leakage current region and a large current region equal to or higher than the leakage current region; a first defect determination means that determines the terminal as a defective terminal if the current value is large, and a first defect determination means that determines the terminal as a defective terminal if the current value after application of the electrostatic pulse fluctuates by more than a predetermined percentage with respect to the initial current value in the large current region; and a second defective determination means for determining a terminal as a defective terminal.

(ホ)作用 この静電破壊試験装置では、先ず電圧設定手段から電圧
供給/電流測定手段を介して、被供試半導体装置の試験
すべき端子と共通基準電位(OND)端子間に設定電圧
が印加される。この設定電圧の印加に応じて流れる電流
が電圧供給/電流測定手段で測定される。設定電圧の数
ポイントに対応する電流値を測定し、この電流値を初期
特性として、特性記憶手段に記憶する。次に、特性測定
用の電圧に代えて、静電パルス用の設定電圧を電圧設定
手段より出力し、これに応答して、静電パルス発生手段
より静電パルスを入力し、前記被供試半導体装置の試験
すべき端子に静電パルスが印加される。この静電パルス
の印加後、電圧設定手段より、再度設定電圧が電圧供給
/電流測定手段を介して、前記試験端子に印加される。
(E) Function In this electrostatic breakdown test apparatus, first, a set voltage is set between the terminal to be tested and the common reference potential (OND) terminal of the semiconductor device under test from the voltage setting means through the voltage supply/current measuring means. applied. The current flowing in response to the application of this set voltage is measured by the voltage supply/current measuring means. Current values corresponding to several points of the set voltage are measured, and these current values are stored in the characteristic storage means as initial characteristics. Next, instead of the voltage for measuring characteristics, a set voltage for electrostatic pulses is output from the voltage setting means, and in response to this, an electrostatic pulse is input from the electrostatic pulse generating means, and the An electrostatic pulse is applied to the terminal of the semiconductor device to be tested. After application of this electrostatic pulse, a set voltage is again applied from the voltage setting means to the test terminal via the voltage supply/current measuring means.

この設定電圧の印加に応じて流れる電流が電圧供給/電
流測定手段で測定される。このような測定が設定電圧の
数ポイントについて行われ、対応する電流値が静電パル
ス印加後の特性として特性記憶手段に記憶される。続い
て、特性記憶手段に記憶される特性が、リーク電流領域
と大電流領域とに電流領域分類手段に分類される。そし
て、リーク電流領域では、初期電流値と静電パルス印加
後の電流値が比較され、静電パルス印加後の電流値が初
期電流値より、さらに所定の基準値以上大である場合に
は、その端子を不良端子と判定する。また、大電流領域
では、初期電流値に対する静電パルス印加後の電流値の
変動割合を算出し、その変動割合が所定以上である場合
に、やはりその端子を不良端子と判定する。
The current flowing in response to the application of this set voltage is measured by the voltage supply/current measuring means. Such measurements are performed at several points of the set voltage, and the corresponding current values are stored in the characteristic storage means as the characteristics after application of the electrostatic pulse. Subsequently, the characteristics stored in the characteristic storage means are classified by the current region classification means into a leak current region and a large current region. Then, in the leakage current region, the initial current value and the current value after applying the electrostatic pulse are compared, and if the current value after applying the electrostatic pulse is larger than the initial current value by a predetermined reference value or more, The terminal is determined to be a defective terminal. Furthermore, in the large current region, the rate of change in the current value after application of the electrostatic pulse with respect to the initial current value is calculated, and if the rate of change is equal to or greater than a predetermined value, the terminal is determined to be a defective terminal.

(へ)実施例 以下、実施例により、この発明をさらに詳細に説明する
(f) Examples The present invention will now be explained in more detail with reference to Examples.

第1図は、この発明の一実施例を示し、自動静電破壊試
験装置を用いて、ICの静電破壊試験を行なう場合の測
定回路図である。同図に於いて、自動静電破壊試験装置
1は試験のための制御を行い、データを記憶するパーソ
ナルコンピュータ(パソコン)2、このパソコン2で設
定される電圧値を出力するデジタルインタフェース3、
この電圧値をアナログ値に変換するD/Aコンバータ4
、アナログ電圧を被供試ICl0に供給し、応じて流れ
る電流を測定する電圧供給/電流測定回路(■フォー 
スエメジャ回路)5、測定された電流値をアナログ値か
らデジタル値に変換してパソコン2に与えるA/Dコン
バータ6、パソコン2の設定静電パルス電圧値を出力す
るデジタルインターフェース7、この電圧値をアナログ
値に変換するD/Aコンバータ8、両極性電源9a、充
電抵抗R、コンデンサC及びスイッチS2からなる静電
パルス発生回路9とから構成されている。
FIG. 1 shows an embodiment of the present invention, and is a measurement circuit diagram when performing an electrostatic discharge test on an IC using an automatic electrostatic discharge test apparatus. In the figure, an automatic electrostatic discharge test device 1 includes a personal computer (personal computer) 2 that performs test control and stores data, a digital interface 3 that outputs voltage values set by the personal computer 2,
D/A converter 4 that converts this voltage value into an analog value
, a voltage supply/current measurement circuit (■Form) that supplies an analog voltage to the ICl0 under test and measures the corresponding current.
5. An A/D converter 6 that converts the measured current value from an analog value to a digital value and provides it to the computer 2. A digital interface 7 that outputs the electrostatic pulse voltage value set for the computer 2. It is comprised of an electrostatic pulse generation circuit 9 consisting of a D/A converter 8 for converting into analog values, a bipolar power supply 9a, a charging resistor R, a capacitor C, and a switch S2.

電圧供給/電流測定回路5と静電パルス発生回路9がス
イッチSlを介して、被供試ICl0の試験ピン(端子
)P、に接続され、自動静電破壊試験装置1のGND端
子と被供試ICl0のGNDピンP6が共通接続されて
設置されている。
The voltage supply/current measurement circuit 5 and the electrostatic pulse generation circuit 9 are connected to the test pin (terminal) P of the ICl0 under test via the switch Sl, and are connected to the GND terminal of the automatic electrostatic discharge test equipment 1 and the test pin (terminal) P of the ICl0 under test. The GND pins P6 of the test ICl0 are connected in common.

自動静電破壊試験装置1は、パソコン2のメモリに種々
の設定電圧が設定可能に構成されるほか、出力される設
定電圧値に対応する電流値も記憶され、いわゆる初期V
−I特性及び、静電パルス印加後のV−1特性も記憶さ
れる。また、静電パルス発生回路9からは、両極性及び
任意の電圧の静電パルスが出力可能である。また、図示
はしていないが、被供試ICl0の試験ピンP、のみな
らず、P z 、P 3 、・・・・、Pl&・・・・
・・と金でのピン端子に、ピン変換マトリクス(リレー
による順次切替回路)を用いて、切替接続し得るように
なっている。
The automatic electrostatic discharge test device 1 is configured such that various setting voltages can be set in the memory of the personal computer 2, and a current value corresponding to the output setting voltage value is also stored, so that the so-called initial V
-I characteristics and V-1 characteristics after electrostatic pulse application are also stored. Furthermore, the electrostatic pulse generation circuit 9 can output electrostatic pulses of both polarities and arbitrary voltages. Although not shown, not only the test pins P of the ICl0 under test, but also P z , P 3 , . . . , Pl & . . .
... and gold pin terminals can be switched and connected using a pin conversion matrix (sequential switching circuit using relays).

次に、上記測定回路により、静電破壊試験を行なう場合
の動作を、第2図に示すフロー図を参照し7て説明する
Next, the operation when performing an electrostatic discharge test using the above measurement circuit will be explained with reference to the flowchart shown in FIG.

先ず、スイッチSIをa側、つまり電圧供給/電流測定
回路5側に投入し、パソコン2より予め設定した電圧値
を、デジタルインターフェース3を通じて出力し、D/
Aコンバータ4でアナログ値に変換して、電圧供給/電
流測定回路5より、被供試ICl0のピンp1に設定電
圧を印加する。
First, switch SI is put on the a side, that is, the voltage supply/current measurement circuit 5 side, and the voltage value preset from the personal computer 2 is outputted through the digital interface 3, and the D/
The A converter 4 converts it into an analog value, and the voltage supply/current measurement circuit 5 applies the set voltage to the pin p1 of the ICl0 under test.

そして、この電圧印加により、流れる電流を電圧゛1ハ
給/電流測定回路5で測定し、この電流値をA/Dコン
バータ6を介して、パソhン2に取込み、設定電圧−電
流値を初期特性として記憶する。この初期特性の測定記
憶は、他のピンP、、P、、。
Then, by applying this voltage, the flowing current is measured by the voltage supply/current measuring circuit 5, and this current value is taken into the personal computer h 2 via the A/D converter 6, and the set voltage - current value is calculated. Stored as an initial characteristic. The measurement memory of this initial characteristic is applied to other pins P,,P,,.

・・・・についても接続を順次切替えて行なう(ステッ
プ5TI)。次にスイッチSlをb側、つまり静電パル
ス発生回路9側に切替え、パソコン2から最初に設定し
た印加電圧値をデジタルインタフェース7を通して出力
し、スイッチS2をb側に切替えて、静電パルス発生回
路9より、ピンPlに静電パルスを印加する。この静電
パルスの印加を他のピンP z 、P z ”””につ
いてもピン切替により順次行なう(ステップ5T2)、
続いて、スイッチS、を再びa側に切替え、設定電圧印
加に対する電流値を測定し、パソコン2のメモリに静電
パルス印加後の電圧−電流特性を記憶する。
. . . are also sequentially switched over (step 5TI). Next, switch Sl is switched to the b side, that is, the electrostatic pulse generation circuit 9 side, and the applied voltage value initially set from the personal computer 2 is output through the digital interface 7, and switch S2 is switched to the b side to generate electrostatic pulses. An electrostatic pulse is applied from the circuit 9 to the pin Pl. Application of this electrostatic pulse is also performed sequentially to other pins P z and P z """ by switching the pins (step 5T2).
Subsequently, the switch S is again switched to the a side, the current value with respect to the application of the set voltage is measured, and the voltage-current characteristic after the application of the electrostatic pulse is stored in the memory of the personal computer 2.

これらの処理も各ピン毎に行なう。そして、記憶した各
ピンの特性値をリーク電流領域か、あるいはリーク電流
領域以上の大電流領域とに分類する。
These processes are also performed for each pin. Then, the stored characteristic values of each pin are classified into a leakage current region or a large current region greater than the leakage current region.

リーク電流領域の判定には、例えば■1μA以下か、あ
るいは■10μAかを使用するが、いずれとするかは、
初期のパラメータで設定する(ステップ5T3)。分類
されたデータがリーク電流領域である場合(ステップ5
T4)、静電パルス印加後の電流値が初期電流値から基
準電流値以上増加しているか否かを判定する(ステップ
5T5)。
To determine the leakage current range, for example, ■ 1 μA or less or ■ 10 μA is used, but which one to use is
Set with initial parameters (step 5T3). If the classified data is in the leakage current region (step 5
T4), it is determined whether the current value after application of the electrostatic pulse has increased by a reference current value or more from the initial current value (Step 5T5).

この基準電流値は、予めパラメータとしてセットされて
いる。ステップST5で基準電流値以上増加している場
合には、そのピンを不良とする。この不良ピンは、次に
静電パルスの印加から除外することになる(ステップ5
T6)。
This reference current value is set in advance as a parameter. If the current has increased by more than the reference current value in step ST5, that pin is determined to be defective. This defective pin will then be excluded from the application of electrostatic pulses (step 5).
T6).

データが大電流領域である場合は、静電パルス印加後の
電流値が初期電流値からA%以上変動したか否か判定す
る(ステップ5T7)。ここで基準とする値Aは、それ
までの故障ICのものより、経験により定め、パラメー
タとしてセットする。
If the data is in the large current region, it is determined whether the current value after application of the electrostatic pulse has varied by A% or more from the initial current value (step 5T7). The reference value A here is determined based on experience from previous failed ICs and is set as a parameter.

ステップST7で、初期電流値からA%以上変動したと
判定されると、そのピンを不良ビンとする。
In step ST7, if it is determined that the current value has changed by A% or more from the initial current value, that pin is determined to be a defective bin.

そして、この不良ビンを、やはり次の静電パルスの印加
から除外する(ステップ5T8)。各ピンにつき、ステ
ップST4〜ST8の処理が終了すると、静電パルスが
最大設定電圧であるか否か判定しくステップ5T9)、
NOの場合には、以前の印加電圧に、所定ステップ電圧
を加えた値の電圧を新たに静電パルスとして、除外不良
ピン以外の各ピンに印加する(ステップ5TIO)。そ
して、ステップST3にリターンし、再度ステップST
3〜ST9の処理を実行する。以後、印加パルスが最大
設定電圧を越えるまで、所定ステップ電圧を加算しつつ
、上記処理を繰り返す。
Then, this defective bottle is also excluded from the application of the next electrostatic pulse (step 5T8). When the processing of steps ST4 to ST8 is completed for each pin, it is determined whether the electrostatic pulse is at the maximum set voltage or not (step 5T9),
If NO, a new electrostatic pulse with a voltage equal to the previously applied voltage plus a predetermined step voltage is applied to each pin other than the excluded defective pins (Step 5TIO). Then, the process returns to step ST3, and step ST3 is performed again.
3 to ST9 are executed. Thereafter, the above process is repeated while adding a predetermined step voltage until the applied pulse exceeds the maximum set voltage.

(ト)発明の効果 この発明によれば、広い領域に亘り、特性試験が可能で
あり、しかもリーク電流領域と大電流領域に分け、リー
ク電流領域は所定値の増加、大電流領域は、百分率の変
動で判定するものであるから、良否を定量的かつ正確に
判定でき、測定者の主観に左右されるなどのおそれはな
い。
(G) Effects of the Invention According to the present invention, characteristics testing can be performed over a wide range, and is divided into a leakage current range and a large current range. Since the determination is based on the fluctuation of the value, the quality can be determined quantitatively and accurately, and there is no fear that it will be influenced by the subjectivity of the measurer.

また、破壊測定にはリーク電流の増加値や電流値の変動
率について、経験に基づくパラメータ設定が可能であり
、フィルドの破壊状態のデータを入れることにより合理
的かつ適切な詳値データを得ることができる。
In addition, for destructive measurements, it is possible to set parameters based on experience regarding the increase in leakage current and the fluctuation rate of current value, and by inputting data on the destructive state of the field, it is possible to obtain reasonable and appropriate detailed value data. Can be done.

また、この発明の装置の機能達成手段に、パソコン等を
使用でき、パソコンの記憶機能、演算機能を十分に活用
し、装置一台で多ピンの静電気破壊耐圧のデータを得る
ことができ、従来の1個のサンプルで1個のデータを出
すというマニュアル測定に比し、格段に合理的な試験が
でき、また試験サンプル数を少なくでき、短時間で判定
出来るという利点がある。
In addition, a personal computer or the like can be used as a means for achieving the functions of the device of this invention, and by fully utilizing the storage and arithmetic functions of the personal computer, it is possible to obtain data on the electrostatic breakdown voltage of multiple pins with a single device. Compared to manual measurement, which generates one piece of data from one sample, this method has the advantage of being able to conduct a much more rational test, reducing the number of test samples, and making decisions in a shorter time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、この発明の一実施例を示す静電破壊試験の測
定回路のブロック図、第2図は、同測定回路による測定
動作を説明するためのフロー図、第3図は、従来の静電
破壊の測定回路を示す回路図、第4図(a)伽)は、試
験ICの端子間の電圧−電流特性の一例を示す図である
。 2:パーソナルコンピュータ。 5:電圧供給/電流測定回路。 9:静電パルス発生回路。 10:被供試IC0 特許出願人     ローム株式会社 代理人  弁理士  中 村 茂 信 第2図 第3図
FIG. 1 is a block diagram of a measurement circuit for an electrostatic breakdown test showing an embodiment of the present invention, FIG. 2 is a flow diagram for explaining the measurement operation by the same measurement circuit, and FIG. A circuit diagram showing a measurement circuit for electrostatic discharge damage, FIG. 4(a)) is a diagram showing an example of voltage-current characteristics between terminals of a test IC. 2: Personal computer. 5: Voltage supply/current measurement circuit. 9: Electrostatic pulse generation circuit. 10: Tested IC0 Patent Applicant ROHM Co., Ltd. Agent Patent Attorney Shigeru Nakamura Figure 2 Figure 3

Claims (1)

【特許請求の範囲】[Claims] (1)予め特性測定用の電圧及び静電パルス発生用の電
圧を設定する電圧設定手段と、この電圧設定手段で設定
される電圧を被供試半導体装置の所定端子と共通基準電
位端子間に印加し、対応して流れる電流値を取込む電圧
供給/電流測定手段と、前記静電パルス発生用の電圧に
応じた静電パルスを発生し、前記特性測定用の電圧に代
えて、前記被供試半導体装置の所定端子に印加する静電
パルス発生手段と、この静電パルスの印加前と、印加後
における前記特性測定用の電圧と電圧供給/電流測定手
段により取込まれる電流値との関係をそれぞれ初期特性
及び静電パルス印加後の特性として記憶する特性記憶手
段と、この特性記憶手段に記憶される特性の電流値をリ
ーク電流領域とリーク電流領域以上の大電流領域とに分
類する電流領域分類手段と、リーク電流領域では、静電
パルス印加後の電流値が初期電流値より所定の基準値以
上大である場合に、その端子を不良端子と判定する第1
の不良判定手段と、大電流領域では静電パルス印加後の
電流値が初期電流値に対し、所定割合以上変動した場合
に、その端子を不良端子と判定する第2の不良判定手段
とを備えたことを特徴とする半導体装置の静電破壊試験
装置。
(1) Voltage setting means for setting the voltage for characteristic measurement and the voltage for electrostatic pulse generation in advance, and the voltage set by this voltage setting means between a predetermined terminal of the semiconductor device under test and a common reference potential terminal. a voltage supply/current measuring means for applying a voltage and taking a correspondingly flowing current value; An electrostatic pulse generation means applied to a predetermined terminal of a semiconductor device under test, and a current value taken in by the voltage for characteristic measurement and voltage supply/current measurement means before and after application of this electrostatic pulse. Characteristic storage means for storing the relationship as an initial characteristic and a characteristic after application of an electrostatic pulse, respectively, and a current value of the characteristic stored in this characteristic storage means is classified into a leakage current region and a large current region equal to or higher than the leakage current region. The current region classification means and the leakage current region include a first method for determining a terminal as a defective terminal if the current value after application of the electrostatic pulse is greater than the initial current value by a predetermined reference value or more.
and a second defect determining means that determines the terminal as a defective terminal if the current value after application of the electrostatic pulse fluctuates by more than a predetermined percentage with respect to the initial current value in a large current region. An electrostatic breakdown test device for semiconductor devices characterized by:
JP62132229A 1987-05-28 1987-05-28 Electrostatic breakdown test equipment for semiconductor devices Expired - Lifetime JPH067154B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62132229A JPH067154B2 (en) 1987-05-28 1987-05-28 Electrostatic breakdown test equipment for semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62132229A JPH067154B2 (en) 1987-05-28 1987-05-28 Electrostatic breakdown test equipment for semiconductor devices

Publications (2)

Publication Number Publication Date
JPS63295981A true JPS63295981A (en) 1988-12-02
JPH067154B2 JPH067154B2 (en) 1994-01-26

Family

ID=15076396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62132229A Expired - Lifetime JPH067154B2 (en) 1987-05-28 1987-05-28 Electrostatic breakdown test equipment for semiconductor devices

Country Status (1)

Country Link
JP (1) JPH067154B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205783B2 (en) 2003-07-08 2007-04-17 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit, and electrostatic withstand voltage test method and apparatus therefor

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6321708Y2 (en) * 1981-06-23 1988-06-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7205783B2 (en) 2003-07-08 2007-04-17 Matsushita Electric Industrial Co., Ltd. Semiconductor integrated circuit, and electrostatic withstand voltage test method and apparatus therefor

Also Published As

Publication number Publication date
JPH067154B2 (en) 1994-01-26

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