JPS63295947A - Defect data entry circuit - Google Patents

Abstract

PURPOSE:To enable accurate entry of defect data, by providing a Y-axis counter, a buffer memory or the like to prevent erroneous recognition of a Y-coordinates position. CONSTITUTION:A start pulse ST and a clock CLK are input inputted into an X-axia counter 11, detect data D11, D12... and D52 are inputted into an OR unit 12 from a defect detector 5 and a line synchronous signal PG is inputted into a frequency dividing circuit 13. A counter 11 counts the clock CL and counts outputs as obtained when a defect data is entered into an FIFO memory 22 as X-coordinates position data. Moreover, a unit 12 accumulates defect data for several scannings corresponding to each of the data D11, D12... and D52, counts the signal PG divided in frequency from the circuit 13, and outputs counts into the memory 22 as Y-coordinates position data when the defect data is inputted. In this manner, an X-coordinate position data, the defect data and the Y-coordinate positions data are stored temporarily into the memory 22. These data are transferred to a CPU7 with a DMA between memory 22 and a memory of the CPU7. This enables accurate entry of the defect data to prevent erroneous recognition at a Y-coordinates position.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a defect data acquisition circuit of a defect detection device, particularly for detecting the type of defect, the size of the defect, and the position of the defect in a transparent plate such as a glass plate. The present invention relates to a defect data acquisition circuit for an identification type defect detection device capable of detecting defects.

[Conventional technology]

When manufacturing transparent plates such as glass plates, the flying spot type is used as a device to detect the type of defects (foreign objects, bubbles, edges, drips, etc.), size, and position of defects that exist on the transparent plate. There is an identification type defect detection device.

FIG. 5 schematically shows an example of an identification type defect detection device developed by the present applicant. This identification type defect detection device makes a laser beam from a laser light source 1 enter a polygonal rotating mirror 2, and scans a laser spot on a glass plate 3 flowing through a manufacturing process line. The scanning direction is a direction perpendicular to the direction in which the glass plate flows (Y-axis direction), that is, the width direction of the glass plate (
(X-axis direction). Further, the laser beam is incident on the surface of the glass plate 3 obliquely. This is to avoid interference between the light reflected from the front surface of the glass plate and the light reflected from the back surface of the glass plate.

Transmitted light and transmitted scattered light 2 of the laser beam incident on the glass plate 3
The reflected light is transmitted to light receivers Di, D2. D3. D4. Receive light at D5. In addition,
Each of these light receivers is constructed by arranging a large number of glass fibers. The light receiver D1 receives transmitted light, the light receiver D2 receives paraxial transmitted scattered light, the light receivers D3 and D4 receive far axis transmitted scattered light, and the light receiver D5 receives reflected light. The glass fibers constituting each photoreceiver are connected to the corresponding photomultiplier tube P.
MI, PM2. PM3. PM4. The light guided and received by the PM5 is converted into an electrical signal by each photomultiplier tube. The signal processing circuit 4 performs differential processing, width processing, and
By adding signal processing such as comparison processing and waveform shaping, defect data D++, D+□, . . . , D, 2 are created. There are multiple types of defect data; for example, defect data D is
This data shows the comparison result of comparing the differential waveform obtained by negatively differentiating the electric signal obtained by photoelectrically converting the transmitted light received by the light receiver D1 with a predetermined detection level.

For convenience of the following explanation, the configuration up to the signal processing circuit 4 is assumed to be the defect detector 5. The defect data from the defect detector 5 is taken in by the defect data acquisition circuit 6 and processed by the central processing unit (CPU). sent to. The CPU 7 creates a defect pattern from the defect data and compares it with a pre-held defect identification pattern table to determine the type, size, etc. of the defect.

The present invention relates to an improvement of the defect data acquisition circuit in such an identification-type defect detection device, but the present invention is not intended only for the above-mentioned identification-type defect detection device, but also applies to flying spot type defect detection devices. If so, any type of identification type defect detection device can be targeted. Further, reflected and scattered light may be further added to the light for detecting a change in light amount.

A conventional defect data acquisition circuit is shown in FIG.

It is assumed that the defect data is output from the defect detector 5 shown in FIG. This fault data acquisition circuit 10 includes an X-axis counter 11, an OR unit 12, and a frequency dividing circuit 13. The X-axis counter 11 is a counter that counts the clock CLK for X-coordinate division, and is reset by a start pulse ST that is a scan start signal. This start pulse ST is obtained by extracting the laser beam reflected by the polygonal rotating mirror 2 of the defect detector 5 with a glass fiber at a specific position, photoelectrically converting it, and shaping the waveform. The X-axis counter 11 outputs the count value when the defect data is taken in as X-coordinate position data.

The OR unit 12 is a unit that stores defect data for multiple scans from the defect detector 5 and outputs it at a predetermined timing. ” is disclosed. The purpose of this OR unit 12 is to increase the processing capacity of the identification type defect detection apparatus in relation to the processing speed of the CPU 7.

The frequency dividing circuit 13 divides the frequency of the line synchronization signal PG corresponding to the moving distance of the glass plate in the line direction and inputs the result to the OR unit 12 . The OR unit 12 outputs the accumulated defect data at the timing of the frequency-divided line synchronization signal PG.

In the conventional defect data acquisition circuit having the above configuration, the defect data stored in the OR unit 2 is transferred to the memory of the CPU 7 by direct memory access (DMA) every time a defect occurs. Therefore, since defect data cannot be captured during DMA, defect data may be missing. In this case, there is a problem that defects cannot be detected.

Furthermore, in the conventional defect data acquisition circuit, the Y-coordinate position of the defect is recognized by software processing on the CPU side. In other words, when data transferred from the import circuit is stored in the memory of the CPU 7, "0" is inserted at each data break, and by counting the number of "0", the position of the Y coordinate is recognized. There is. However, in this method, since the memory capacity of the CPU 7 is limited, there is a problem that the Y coordinate position may be incorrectly recognized once the storage has finished.

SUMMARY OF THE INVENTION An object of the present invention is to provide a defect data acquisition circuit for an identification type defect detection device that solves the above-mentioned problems.

[Structure of the invention]

The present invention scans a transparent plate running in the length direction with a light spot in the width direction, and based on the combination of changes in the light amount of any one of transmitted light, transmitted scattered light, reflected light, 9 reflected scattered light. In the defect data acquisition circuit of the identification type defect detection device that detects the type, size, and position of the defect, the first pulse train related to the position in the width direction of the transparent body is counted, and the defect data is acquired. a first counter that outputs a counted value when defect data is taken in; and a second counter that counts a second pulse train related to a position in the length direction of the transparent body and outputs a counted value when defect data is captured a counter, an OR unit that stores defect data for multiple scans and performs OR processing, and outputs the processed defect data at the pulse generation timing of the second pulse train; the X-axis counter, the Y-axis counter, and the OR unit; It is characterized by being equipped with a buffer memory for temporarily storing the output of.

〔Example〕

The present invention will be explained in detail below.

FIG. 1 is a bronc diagram showing one embodiment of the present invention. It is assumed that the defect data is input from the defect detector 5 shown in FIG. This defective data acquisition circuit 20 is
In the conventional defect data acquisition circuit shown in FIG.
Furthermore, a Y-axis counter 21 is installed after the frequency dividing circuit 13,
Axis counter 11. OR unit 12. Y-axis counter 21
A FIFO memory 22 is added at the subsequent stage. Y
The axis counter 21 counts the frequency-divided line synchronization signal PC from the frequency dividing circuit 13, and when inputting defect data, stores the count value as Y-coordinate position data in the FIFO memory 22.
Output to. Note that the Y-axis counter 21 is reset by software. The FIFO memory 22 temporarily stores X-coordinate position data from the X-axis counter 11, defect data from the OR unit 12, and Y-coordinate position data from the Y-axis counter 21. Then, defect data and defect position data (X.

Y) is transferred to the memory of the CPU 7 by DMA.

FIG. 2 shows an example of the OR unit 12. This OR unit 12 generates multiple types of defect data D++, D+□.

..., logical sum circuit OR, respectively corresponding to DSz,
,,OR,□,...,OR,2, and the random access memory RAM r In RAM + t,
..., RAM5z and gate circuit G11. G+z+
..., G, 2.

3 and 4 are diagrams to help understand the operation of the OR unit 12, and FIG. 3 shows the relationship between scanning by a laser spot and the clock CLK and line synchronization signal PC after frequency division. The schematic diagram in FIG. 4 is a diagram showing a state in which defect data D is stored in RAM+I of the OR unit. Please refer to these drawings to make the OR unit)12
As an example, the operation of storing the defect data D11 will be explained. It is assumed that the glass plate is scanned n times in the X-axis direction by the laser spot during the frequency-divided line synchronization signal PG. Further, it is assumed that each RAM of the OR unit 12 has addresses up to 1000. The address of each RAM corresponds to the number of clocks CLK is.

Now, when there is a defect 40 on the glass plate 3 as shown in FIG. 3, the defect data DIl inputted from the defect detector 5 in the first scan is written to RAM + + and stored at addresses 502 and 503. The focus is "1". The defect data D11 inputted in the second scan is ORed with the defect data read out from the RAM 11 in the OR circuit 0R11, and then rewritten to the RAM + +,...nth scan. Defect data D input by scanning
After the fault data read from RAM r + is ORed in the logical sum circuit OR8,
++ is rewritten, and bit "l" is finally stored at addresses 501 to 504. Defect data D1 stored in RAM + + in this way
1 is a gate circuit G at the timing of the line synchronization signal PG frequency-divided by the frequency divider circuit 13;

It is output after passing through.

As a result of the processing in the OR unit 12 as described above, defects that are close to each other in the Y-axis direction are regarded as the same defect, and as a result, the amount of information to be processed by the CPU can be reduced.

As a result, the speed of inspection can be increased by increasing the traveling speed of the glass plate, or, if the traveling speed of the glass plate remains the same, the detection sensitivity can be improved several times by reducing the laser spot diameter.

Now, returning to FIG. 1, the operation of the defect data acquisition circuit of this embodiment will be explained in more detail. The X-axis counter 11 receives a start pulse ST and a clock CLK, and the OR unit 12 receives defect data Dllll Dl! from the defect detector 5. ,...

Ds! is input, and the line synchronization signal P is input to the frequency dividing circuit 13.
G is input. The X-axis counter 11 receives the clock CLK
is counted, and the count value when the defect data is taken in is output to the PIF0 memory 22 as X coordinate position data. , the X-axis counter 11 receives the start pulse signal ST.
It is reset by .

As explained in FIG. 3 and FIG.
..., D,, accumulates defect data for multiple scans,
It is output to the FIFO memory 22 at the timing of the line synchronization signal PG frequency-divided by the frequency dividing circuit 13.

The Y-axis counter 21 counts the frequency-divided line synchronization signal PG from the frequency dividing circuit 13, and when defect data is input,
FIFO memory 2 uses count value as Y coordinate position data
Output to 2. Note that the Y-axis counter 21 is reset by software.

As mentioned above, the X coordinate position data and defect data.

The Y coordinate position data is temporarily stored in the FIFO memory 22, and these data are transferred to the memory of the CPU 1 by DMA between the FIFO memory 22 and the memory of the CPU 7. This data transfer is performed in accordance with the data processing speed of the CPU 7. Therefore, it is possible to reliably capture all defect data without being able to capture defect data during DMA, which is the case with conventional defect data capture circuits, thereby preventing defect data from being missing.

In addition, by providing the Y-axis counter 21, detection of the Y-coordinate position data, which was conventionally performed by software processing, is now performed by hardware processing. The problem of misidentification will disappear.

〔Effect of the invention〕

As explained above, according to the defect data acquisition circuit of the present invention, a Y-axis counter is provided and the detection of the Y-coordinate position data of the defect is performed by hardware, so that it can be processed similarly to conventional software processing. This eliminates the possibility of erroneously recognizing the Y-coordinate position of a defect.

In addition, a buffer memory is provided to store faulty data.

Since the Y-coordinate position data and Y-coordinate position data are temporarily stored in the puffer memory, the defect data can be reliably imported. There is no longer any fear that it will be missing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the OR unit in FIG. 1, and FIGS. 3 and 4 explain the operation of the OR unit. FIG. 5 is a block diagram showing an outline of an identification type defect detection device, and FIG. 6 is a block diagram showing a conventional defect data acquisition circuit. 1... Laser light source 2... Polygonal rotating mirror 3... Glass plate 4... Signal processing circuit 5... Defect detector 6 , 10.20...Fault data acquisition circuit 7...
・CPU 11...X-axis counter 12...OR unit 13...Divide circuit 21...Y-axis counter 22...FIFO memory 40...Flaws

Claims (1)

[Claims] (1) A transparent plate running in the length direction is scanned with a light spot in the width direction, and defects are detected based on the combination of light intensity changes of transmitted light, transmitted scattered light, reflected light, and reflected scattered light. In a defect data acquisition circuit of an identification type defect detection device that detects the type, size, position, etc. of a first counter that outputs a counted value; and a second counter that counts a second pulse train related to the longitudinal position of the transparent plate and outputs a counted value when defect data is taken in. an OR unit that stores and OR-processes defect data for multiple scans and outputs the processed defect data at the pulse generation timing of the second pulse train; and the X-axis counter, Y-axis counter, and OR unit. A defective data acquisition circuit characterized by comprising a buffer memory for temporarily storing output.