JPS6329578A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the leak current generated at the junction between the high impurity density region, formed by the channel doping for writing-in of information and a drain region, and the drain region as well as to increase the threshold voltage after information has been written in by a method wherein the drain region of an MISFET is deeply formed in such a manner that the distribution of impurity density will be made gentle. CONSTITUTION:BF2, for example, is ion-implanted into a semiconductor substrate 1 in the state wherein a photoresist is covered on the whole surface excluding the surface on the side of an n-well 2, and after a p<+> type source region 16 and a drain region 17 have been formed, the ion-implanted n-type and p-type impurities are diffused by performing an annealing process, and said regions are electrically activated. In this case, as the source region 12 and the drain region 13 of the MISFET 18 are formed using the phosphorus having a high diffusion velocity, these regions 12 and 13 can be formed deeper than annealing, and the impurity density is distributed gently both in depth direction and lateral direction. Through the above-mentioned procedures, the reduction in leak current at the junction between the high impurity density region formed by channel doping and the drain region can be achieved, and the threshold voltage after writing-in of information of the MISFET can also be made higher.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a mask R.
The present invention relates to a technique that is effective when applied to writing information into an OM (Read Only Memory) memory cell.

[Conventional technology]

In mask ROM, usually MI S F E T
A memory cell is configured, and information is written into the memory cell by controlling the threshold voltage of the MISFET. and for example a MISFE with a low threshold voltage (e.g. 0.5V)
T corresponds to information “l”, and M I S F E T with a high threshold voltage (for example, 3V) corresponds to information “°”.
O'° is made to correspond.

One method of controlling the threshold voltage of the MISFET is, for example, a method of implanting impurity ions (channel doping) into the channel portion of the MISFET, as described in Japanese Unexamined Patent Publication No. 56-130963. Are known.

The inventor studied a method of writing information into memory cells of a mask ROM. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

In other words, writing information into the memory cells of the mask ROM requires a turnaround time (turnaround time), which is the time required to complete the mask ROM into which desired information has been written.
In order to shorten the manufacturing process of the mask ROM, this process is performed after the formation of the A1 wiring, which is the final process of the mask ROM manufacturing process. In other words, the MISFET that constitutes the memory cell
After forming, the process proceeds to the formation of an interlayer insulating film, and after forming the A1 wiring, boron ions are implanted into the channel part of the MISFET that constitutes the memory cell in which information is to be written, via the interlayer insulating film. Channel doping is performed, and then annealing is performed to recover crystal damage caused by this ion implantation and to electrically activate the ion implanted impurities. In this case, A1 with a low melting point
Since the wiring has already been formed, this annealing is performed at a low temperature of, for example, about 450°C.

[Problem that the invention seeks to solve]

The higher the threshold voltage (higher threshold voltage) of the MISFET corresponding to the above information "o" is, the better in order to make it easier to distinguish it from the information "1"; for example, if a value of 4■ or more is desired. There is. In order to increase the threshold voltage in this way, the dose of channel doping must be increased. However, when channel doping is performed after forming Al interconnects, only low-temperature annealing can be performed as described above, so if the dose of channel doping is high, it is difficult to sufficiently recover crystal damage caused by impurity ion implantation. becomes.

Further, since the source region and drain region of the MISFET described above are formed by arsenic ion implantation, the impurity concentration distribution in these source regions and drain regions is steep.

Furthermore, boron ions implanted for information writing are placed in the channel area directly under the gate insulating film.

It is highly concentrated in the regions immediately below the source and drain regions. Therefore, the electric field at the junction between this high impurity concentration region and the drain region having a steep impurity concentration distribution is large.

For these reasons, there is a problem in that there is a large amount of leakage current at the junction between the high impurity concentration region formed by channel doping and the drain region.

An object of the present invention is to provide a technique that can reduce leakage current at a junction between a drain region and a high impurity concentration region formed by channel doping for information writing.

Another object of the present invention is to provide a technique that can increase the threshold voltage of M 73 FET after information is written.

The above and other objects and novel features of the present invention are the present invention! l! This will become clear from the description of Anzu and the attached drawings.

[Means for solving problems]

An overview of one typical invention disclosed in this application is as follows.

That is, the drain region of the MISFET is provided deep so that the impurity concentration distribution is gentle.

[For production]

According to the above means, since the junction between the high impurity concentration region formed by channel doping for information writing and the drain region becomes a gently sloped junction, it is possible to relax the electric field at this junction. Therefore, it is possible to reduce the leakage current of the junction. In addition, since it is possible to reduce the leakage current of the junction in this way, it is possible to increase the dose of channel doping for information writing, which reduces the threshold value of the MI S FET after information writing. It becomes possible to increase the voltage.

〔Example〕

Hereinafter, the configuration of the present invention will be described based on one embodiment with reference to the drawings.

In addition, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

For convenience of explanation, a method for manufacturing a mask ROM according to this embodiment will be explained first.

As shown in FIG. 1, first, an n-type impurity such as phosphorus is added to a semiconductor substrate 1 such as a p-type S1 substrate at a dose of (5 to 6)XIO''/cd (impurity concentration of approximately 1. An n-well 2 is formed by ion implantation under conditions of approximately 6 x 10"#j), and then a field insulating film 3 such as a 5i02 film is formed on the surface of the semiconductor substrate 1 by selective oxidation to perform element isolation. After that, a gate insulating film 4 such as a SiO2 film is formed on the surface of the active region surrounded by the field insulating film 3 by, for example, thermal oxidation.
form. Note that in FIG. 1, the area indicated by A is an area that will become a memory cell section, and the area indicated by B is an area that will become a peripheral circuit section (the same applies hereinafter).

Next, a P-type impurity such as boron is implanted with an energy of 30 keV (for example, 60 keV in the case of BF2).
ion implantation into the entire surface under conditions of a dose of about 1×10 I2/Cl1f. This allows the n-channel MIS, which will be described later, to configure memory cells and peripheral circuits, respectively.
The threshold voltage of the FETs 18 and 19 is set to, for example, about 0.55V, and the threshold voltage of a P-channel MISFET 20, which will be described later, formed in the n-well 2 is set to, for example, about -0.55V.

Next, for example, a polycrystalline silicon film is formed on the entire surface by, for example, CVD, and the polycrystalline silicon film is doped with impurities by diffusion, ion implantation, etc. to lower its resistance, and then the polycrystalline silicon film is etched into a predetermined shape. As shown in FIG. 2, word lines 5 for memory cells and gate electrodes 6.7 of MISFETs 19 and 20 for peripheral circuits are formed. Note that the word line 5 and the gate electrode 6.7 are formed on a polycrystalline silicon film by, for example, W S
It is also possible to have a structure in which a high melting point metal silicide film such as an i 2 film is provided.

Next, the entire surface except the upper part of the active region where the gate electrode 6 is provided (the n-channel MISFET formation region of the peripheral circuit) is covered with, for example, a photoresist (not shown), and the gate electrode 6 is used as a mask. By implanting n-type impurities, such as phosphorus, into the semiconductor substrate 1 under conditions such as implantation energy of 50 keV and dose of about 1xlO13/aJ, a cell phase is formed with respect to the gate electrode 6, as shown in FIG. An i-type semiconductor region 8 is formed in a line. Note that the n-type impurity ion implantation may be performed in the region A that will become the memory cell portion. Thereafter, the entire surface of the n-well 2 except for the surface is covered with, for example, a photoresist (not shown), and in this state, using the gate electrode 7 as a mask, implantation is performed into the semiconductor substrate l at an energy of 60 keV and a dose of 1 l x 10''/ cn
By ion-implanting, for example, BF2 under conditions of approximately f, a P- type semiconductor region 9, for example, is formed in the self-alignment line with respect to the gate ff electrode 7.

Next, an insulating film such as a SiO2 film is formed on the entire surface by, for example, CVD, and then anisotropic etching is performed in a direction perpendicular to the substrate surface until the surface of the semiconductor substrate 1 is exposed, for example, by reactive ion etching (RIE). By doing this, side walls 10 made of an insulator are formed on the side surfaces of the word line 5 and the gate electrode 6.7, as shown in FIG. After this.

By slightly thermally oxidizing the surface of the semiconductor substrate 1, a thin S
An insulating film 11 such as an iO2 film is formed.

Next, with the entire surface of the region A that will become the memory cell portion except for the surface covered with, for example, a photoresist (not shown), implantation energy is increased to
By ion-implanting, for example, phosphorus into the semiconductor substrate 1 under conditions of keV and a dose of 1×10 14 to 1 form.

Next, with the active region (P-channel MISFET forming region of the peripheral circuit) in which the gate electrode 7 is provided covered with, for example, a photoresist (not shown), implantation is performed using, for example, the side wall 10 as a mask with an implantation energy of 80 keV and 1X.
By implanting, for example, arsenic ions into the semiconductor substrate 1 under conditions of about 10''/cj, an n-channel MISFET for the memory cell section and peripheral circuits is formed as shown in FIG.
A 1' type source region 14 and a drain region 15 are formed in the second region. Note that the arsenic ion implantation does not need to be performed by covering the memory cell portion with photoresist. The n-type semiconductor region 8 shown in FIG. 4 constitutes a part of these source regions 14 and drain regions 15, so in FIG.
Indicated by a (the same applies below). Next, with the entire surface except the surface on the n-well 2 side covered with, for example, a photoresist (not shown), implantation is performed using the side wall 10 as a mask, for example, at an energy of 80 keV and a dose of 2 X l O+s/.
By implanting ions of, for example, B P 2 into the semiconductor substrate 1 under conditions of approximately d, an i-type source region 1 is formed.
6 and a drain region 17 are formed.

Note that the P-type semiconductor region 9 shown in FIG. 4 constitutes a part of these source regions 16 and drain regions 17, so in FIG. 5, these are indicated by symbols 16a and 17a (the same applies hereinafter) . After this, for example, 10 minutes at a temperature of 950℃.
Annealing is performed for about 30 minutes to diffuse the ion-implanted n-type and p-type impurities and to electrically activate them. In this case, the source region 12 and drain region 13 of the MISFET 1B are formed from phosphorus, which has a high diffusion rate as described above, and therefore are formed deeply by the annealing, and the impurity concentration distribution is in the depth direction (perpendicular to the substrate surface). direction) and the lateral direction (direction parallel to the substrate surface).

Note that the gate electrode consisting of the word line 5 and the source region 12
and the drain region 13 constitute the memory cell.
A channel MISFET 18 is configured. In addition, the gate electrode 6, the source region 14, and the drain region 15
A channel MISFET 19 is configured, and a gate electrode 7,
The source region 16 and drain region 17 constitute a P-channel MI 5FET 20. And these n-channel MISFET19 and P-channel MISFE
A peripheral circuit is constituted by the CMO3 made up of T20. Note that the MISFET19.20 for peripheral circuits
is a so-called L D D in which low impurity concentration regions 15a and 17a are provided in these drain regions 15.17 in order to alleviate the electric field near )'L/e[vi15.17.
(Lightly Doped Drain) structure. The mask ROM according to this embodiment can also be adapted to the case where the peripheral circuit is constituted by the MISFETs 19 and 20 having the LDD structure. Note that the peripheral circuit 1 does not necessarily have to be composed of MISFETs with an LDD structure. 6. Next, as shown in FIG. After forming this interlayer #P
! , the edge @21 and predetermined portions of the insulating film 11 are removed by etching to form contact holes 21a to 21d. Note that the annealing can also be performed after the interlayer insulating film 21 is formed.

Next, for example, A1 is coated on the entire surface by sputtering, vapor deposition, etc.
After forming the film, the A1 film is patterned into a predetermined shape by etching to form electrodes 22-24.

Next, as shown in FIG. 6, the entire surface of the MISFET, for example, MISFET 18, which constitutes the memory cell in which information "'0" is to be written, is covered with a photoresist 25, as shown in FIG. Interlayer insulation film 2
1. By ion implanting, for example, boron into the channel portion of the MISFET 18 via the word line 5 etc. under the conditions of implantation energy of 300 keV and dose of about 2×10”/cd, the threshold voltage is set to 4 V, for example.
Information is written at a higher level than normal. Note that the peak position of the distribution of ion-implanted boron is shown by a dashed line in FIG.

After this, the photoresist 25 is removed and then, for example, H
By performing low temperature annealing in 2, the desired mask ROM is completed.

Mask RO according to this example manufactured as described above
A-A line and B-B line (
Figure 6) shows an example of the impurity concentration distribution along the gate M!
The interface between the edge film 4 and the semiconductor substrate 1 is taken as the origin and shown in FIGS. 7 and 8, respectively.

As can be seen from these figures 7 and 8, the peak of the distribution of boron introduced by channel doping is
It is located directly under the gate insulating film 4 and inside the drain region 13 . Therefore, as in the technique studied by the present inventors, no junction is formed between the drain region and the high concentration boron doped region formed directly below the drain region by channel doping.

Further, although not shown, the impurity concentration distribution in the lateral direction of the drain region 13 is also gentle as shown in FIG. 8. Therefore, the junction between the high concentration boron doped region formed in the channel portion and the drain region 13 is a gently sloped junction (g
The electric field at this junction can be effectively relaxed, thereby reducing the leakage current at this junction. Therefore, the reliability of the mask ROM can be improved.

Furthermore, since the junction leakage current can be reduced in this way, the boron channel doping dose for information writing can be reduced to, for example, 2×10 13 as described above.
/Cl11, which allows M
As described above, the threshold voltage of the ISFET 18 after information is written can be made as high as, for example, about 4■ or more.

In addition, since the threshold voltage after information writing can be increased in this way, it becomes easy to determine the information "'1" and "o" written in the MISFET 18, and therefore the threshold voltage after information writing can be increased. The process of determining information becomes easier than when the voltage is low. Therefore, high-speed reading of information is possible.Furthermore, since information is written after forming the A1 electrode as described above, the turnaround time can be shortened.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention can be applied to various semiconductor integrated circuit devices 1, such as microcomputers, including a mask ROM.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects obtained by typical inventions will be briefly explained.

It is as follows.

That is, it is possible to reduce the leakage current at the junction between the high impurity concentration region formed by channel doping and the drain region, and it is also possible to increase the threshold voltage of the MISFET after information is written.

[Brief explanation of drawings]

1 to 6 show a mask RO according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view for explaining an example of a method for manufacturing M in the order of steps. FIG. 7 is a graph showing an example of the impurity concentration distribution along line A-A in FIG. 6, with the interface between the gate insulating film and the semiconductor substrate as the origin, and FIG. 8 is a graph showing B-B in FIG. 6. 7 is a graph showing an example of impurity concentration distribution along a line with the interface between the gate insulating film and the semiconductor substrate as the origin. In the figure, l: semiconductor substrate, 2: n-well, 5: word line, 6.7: gate electrode, 10: side wall, 12.14
．． 16- Source region, 13.15.17 Drain region, 18.19- n-channel MISFET, 20.
・P-channel MISFET, 21...Interlayer insulating film, 2
2 to 24 electrodes, 25 photoresist.゛(X゛Figure 1 Figure 2 Figure 3 Figure Dotsu°(χ-n nu9 7(P) 笥4
figure

Claims (1)

[Claims] 1. Equipped with a plurality of memory cells composed of MISFETs,
A semiconductor integrated circuit device in which information is written into the memory cell by controlling the threshold voltage of the MISFET, wherein the drain region of the MISFET is provided deep so that the impurity concentration distribution is gentle. Features of semiconductor integrated circuit devices. 2. The semiconductor integrated circuit device according to claim 1, wherein the drain region of the MISFET is formed by ion implantation of phosphorus. 3. The semiconductor integrated circuit device according to claim 1 or 2, wherein the drain region of the MISFET is formed deeper than the peak concentration depth of the ion-implanted layer for threshold voltage control. 4. The semiconductor integrated circuit device according to any one of claims 1 to 3, wherein the semiconductor integrated circuit device is a mask ROM.