JPS6325966A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To shorten a turnaround time, to prevent decrease in withstanding voltage at the junction in an MISFET and to make it possible to decrease leakage current from the junction, by performing channel doping for writing information in a memory cell after the formation of an interlayer insulating film and before or after the formation of interconnections, and performing annealing with microwave irradiation. CONSTITUTION:Channel doping for writing information in a memory cell comprising a MISFET is performed after the formation of an interlayer insulating film and before or after the formation of interconnections SL and DL. Then, annealing with microwave irradiation is performed. For example, on a semiconductor substrate 1, a field insulating film 2, a gate insulating film 3, word lines WL1 and WL2, n<+> type semiconductor regions 4 and 5, an interlayer insulating film 6, contact holes 6a-6c, source lines SL1 and SL2 and a data line DL are formed. Only the interlayer insulating film 6 at the upper part of the channel part of MISFET Q1, in which information '0' is to be written, is exposed. The other part of the surface is covered with a photoresist film 7, and channel doping is performed. The thereshold voltage value of the MISFET Q1 is set at a high value. Then annealing with microwave irradiation is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and particularly to a method for manufacturing a mask ROM (Read Only Memory).
) relates to a technique that is effective when applied to writing information into memory cells.

[Conventional technology]

In a mask ROM, a memory cell is usually configured with a MISFET, and information is written into the memory cell by controlling the threshold voltage of the memory MISFET. For example, information "1" is associated with an MI S FET having a low threshold voltage, and information II O11 is associated with an MI S FET having a high threshold voltage.

As a method for controlling the threshold voltage of the MISFET,
For example, as described in Japanese Unexamined Patent Publication No. 56-130963, a method of implanting impurity ions (channel doping) into the channel portion of a MISFET is known.

The inventor studied a method of writing information into memory cells of a mask ROM. Although the following is not a publicly known technique, it is a technique studied by the present inventor, and its outline is as follows.

Writing information into the memory cells of the mask ROM takes the time required to complete the mask ROM in which desired information has been written.
In other words, turnaround time
Mask ROM
After forming the wiring, which is the final step of the 12 manufacturing process, that is, after forming the MISFET that constitutes the memory cell, proceeding to the step of forming the ya insulating film, and further forming the aluminum (AI) wiring, In this case, channel doping is performed by ion implantation for information writing through the interlayer insulating film, and then annealing is performed to recover crystal damage caused by ion implantation and to electrically activate the ion implanted impurities. , since the A1 wiring has already been formed, this annealing is performed for example 4 times.
This is done at a low temperature of around 50°C.

[Problem to be solved by the invention] MI S FET corresponding to the above information 1#071
The higher the threshold voltage (higher threshold voltage) is, the better it is in order to make it easier to distinguish information from "B".However, in order to increase the threshold voltage, the channel doping dose must be adjusted It has to be expensive.

This tendency becomes more pronounced as the gate insulating film becomes thinner. However, when channel doping is performed after forming Al interconnects, as mentioned above, only low-temperature annealing can be performed and the electrical activation rate of impurities is low, so the channel doping dose must be increased. Savings
There is a problem in that the breakdown voltage of the junction between the drain region and the channel portion of the MISFET decreases. Furthermore, since it is difficult to sufficiently recover crystal damage caused by ion implantation with low-temperature annealing, there is a problem in that there is a large leakage current at the junction between the drain region and the channel region.

An object of the present invention is to provide a technique that can shorten turnaround time.

Another object of the present invention is to provide a technique capable of preventing deterioration of the junction breakdown voltage of a MISFET caused by channel doping for writing information and reducing junction leakage current.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

Outline of typical inventions disclosed in this application is as follows.

That is, channel doping for writing information into the memory cell is performed after the interlayer insulating film is formed and before or after the wiring is formed, and then annealing is performed using microwave irradiation.

[For production]

According to the above means, annealing by microwave irradiation can increase the electrical activation rate of channel-doped impurities and can sufficiently recover crystal damage caused by channel doping. It is possible to prevent the breakdown voltage of the junction from deteriorating and to reduce the leakage current of the junction, and also to shorten the turnaround time.

〔Example〕

Hereinafter, the configuration of the present invention will be described based on embodiments with reference to the drawings.

In addition, in all the figures, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

For convenience of explanation, the configuration of a completed mask ROM manufactured according to this embodiment will first be described.

As shown in FIGS. 1 and 2, in the mask ROM manufactured according to the two embodiments, one is
i) A field insulating film 2, such as a SiO2 film, is provided on a semiconductor substrate 1, such as a substrate, to perform element isolation. Code W L s , W L 2
are word lines provided on the gate insulating film 3, such as a SiO* film, and each of these is made of a polycrystalline Si film doped with an impurity such as phosphorus.

On the other hand, in the semiconductor substrate 1, the word lines WL1, WL
2, an n0 type semiconductor region 4.5 is provided in the self-line. Then, the word line WLs and the n" type semiconductor regions 4 and 5 are used as gate electrodes, source regions, and drain regions, respectively, and MI S F E T Q 5,
Q* is configured. Similarly.

The word line WL2. M
I S F E TQs, Q4 are configured.

Further, the n-type semiconductor region 4.5. Word line WL□
, WL2, etc., for example, phosphorus silicate glass (P
An interlayer insulating film 6 such as a SG) film is provided to cover these. Note that in FIG. 1, illustration of the interlayer insulating film 6 is omitted to make it easier to understand the structure of the mask ROM. and.

Contact holes 6a~ provided in this interlayer insulating film 6
Source line SLs made of 1, for example, A1 film through 6C
, Si2, and data line DL (all indicated by dashed-dotted lines in FIG. 1) are in contact with the n-type semiconductor regions 4 and 5, respectively.

Next, a method of manufacturing a mask ROM according to this embodiment will be explained.

First, as shown in FIG. 1, a field insulating film 2 is formed on a semiconductor substrate l by, for example, selective oxidation.

Next, the surface of the active region surrounded by the field insulating film 2 is thermally oxidized to form, for example, 5iOz, as shown in FIG.
After forming the gate insulating film 3 like a film, channel doping is performed by implanting low concentration ions such as boron (B) into the semiconductor substrate 1 through the gate insulating film 3. The threshold voltage of all MISFETs constituting the circuit is set to a low threshold voltage (for example, 0.5 V). Next, for example, polycrystalline Si is deposited on the gate insulating film 3 by, for example, the CVD method.
After forming the film, it is diffused into this polycrystalline Si film.

The resistance of this polycrystalline Si film is lowered by doping impurities such as phosphorus by ion implantation or the like. Next, this polycrystalline Si film is patterned into a predetermined shape by etching to form words gwL1. Form WL2. Note that these word lines WL1. WL* may have a structure in which a high melting point metal silicide film such as MoSi2 film or WSi2g is provided on a polycrystalline Si film.Firstly, using these word lines WL+ and WL2 as a mask, a film is formed in the semiconductor substrate l. For example, after doping an n-type impurity such as arsenic (^S) at a high concentration by ion implantation or the like, annealing is performed to electrically activate the impurity, thereby forming an n°-type semiconductor region 4.5. . After this, the word line W L 1. The gate insulating film 3 other than the portion below W L 2 is removed.

Next, as shown in FIG. 5, an interlayer insulating film 6 such as PSGI is formed on the entire surface by, for example, a CVD method, and then a predetermined portion of this glabellar insulating film 6 is removed by etching to form contact holes 6a to 6C. do. Note that the ya interlayer insulating film is made of silicate glass containing boron and phosphorus.
A (Boro-Phosph.

A glass film) or other insulating film may also be used. Next, after forming, for example, an Al film on the entire surface by sputtering, vapor deposition, etc., this A1 film is patterned into a predetermined shape to form sources McSL+, SL2, and data lines DL. After covering the other parts with a photoresist film 7 so that only the upper part of the channel part of the memory cell to be written, for example, MI 5FETQI, is exposed, a film of, for example, boron is applied using the photoresist film 7 as a mask. Channel doping is performed by ion implantation of p-type impurities such as
The threshold voltage of E T Q + is set to a high threshold voltage.

After performing the ion implantation described above, the photoresist film 7
6. Next, annealing is performed, for example, by microwave irradiation in an inert gas.

In this case, the data line DL and the source line SLY.

The portions of the semiconductor substrate 1 not covered with Si2 are selectively heated by microwave irradiation, and annealing is effectively performed. This makes it possible to increase the electrical activation rate of the ion-implanted impurities, so M
The dose of channel doping for setting the I5FETQ+ to a high threshold voltage can be reduced by this amount. Therefore, deterioration of breakdown voltage can be prevented. Further, this annealing using microwave irradiation can sufficiently recover crystal damage caused by ion implantation, and therefore leakage current of the junction can be reduced. Furthermore, since the leakage current can be reduced in this way, the margin of the power supply potential VCC of the data line DL can be increased.

After that, by performing low-temperature 7-annealing in H2 for example, the target mask R is formed as shown in FIGS. 1 and 2.
Complete the OM.

According to the mask ROM manufacturing method according to this embodiment, channel doping for writing information into memory cells is performed after wiring formation, which is the final step of the mask ROM manufacturing process, so that desired information can be written. Mask R
OM can be manufactured in a short time. In other words, the turnaround time can be shortened.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in the above embodiment, the channel doping for writing information is performed on the data line DL made of Alg.
1. For example, the channel doping may be performed after the formation of the interlayer insulating film 6 and before the formation of the data line DL, etc., and then annealing by microwave irradiation may be performed in the same manner as in the above embodiment. effect can be obtained. Furthermore, the present invention can be applied to various semiconductor integrated circuit devices including mask ROMs.

〔Effect of the invention〕

A brief explanation of the effects obtained by one representative invention among the inventions disclosed in this application is as follows.

In other words, it is possible to prevent deterioration of the junction breakdown voltage of the MISFET and reduce junction leakage current, and
It is possible to shorten the turnaround time.

[Brief explanation of drawings]

FIG. 1 is a plan view of a mask ROM manufactured by a method for manufacturing a mask ROM according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line A-A in FIG. 1. FIGS.
FIG. 3 is a cross-sectional view for explaining the manufacturing method of M in the order of steps. In the figure, 1... semiconductor substrate, 3... gate insulating film, 6
...Interlayer insulating film, 7... Photoresist film, WL+
, WL2...word line, SL+, SL2...source line, agent patent attorney Katsuo Ogawa (',,,'',,,
. Figure 1 Figure 2

Claims (1)

[Claims] 1. Equipped with a plurality of memory cells composed of MISFETs,
A method for manufacturing a semiconductor integrated circuit device in which information is written in the memory cell by controlling the threshold voltage of the MISFET, the method comprising forming an interlayer insulating film to perform channel doping for writing the information in the memory cell. 1. A method for manufacturing a semiconductor integrated circuit device, characterized in that annealing is performed later before or after wiring formation, and then annealing is performed by microwave irradiation. 2. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the wiring is an aluminum wiring. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1 or 2, wherein the semiconductor integrated circuit device is a mask ROM.