JPS63294130A - Digital/analog converter - Google Patents

Digital/analog converter

Info

Publication number
JPS63294130A
JPS63294130A JP13090187A JP13090187A JPS63294130A JP S63294130 A JPS63294130 A JP S63294130A JP 13090187 A JP13090187 A JP 13090187A JP 13090187 A JP13090187 A JP 13090187A JP S63294130 A JPS63294130 A JP S63294130A
Authority
JP
Japan
Prior art keywords
converter
constant
digital
adder
offset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13090187A
Other languages
Japanese (ja)
Inventor
Hiroshi Sugano
宏 菅野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP13090187A priority Critical patent/JPS63294130A/en
Publication of JPS63294130A publication Critical patent/JPS63294130A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To reduce the distortion produced at the time of small signals, by constituting a digital/analog (D/A) converter of a constant multipier and constant adder, which make digital operations, D/A converter, and band-pass filter. CONSTITUTION:This D/A converter is constituted of a constant multiplier 2 and constant adder 3, which make digital operations, D/A converter 4, and band-pass filter 5. The constant multiplier 2 multiplies digital signals inputted from an input terminal 1 by a constant and the constant adder 3 adds a DC offset to the digital signals. Then the D/A converter 4 performs D/A conversion on the output of the adder 3, but, since the digital signals have the offset and the signals after the offset do not cross the bipolar-zero point of the D/A converter 4, large distortion is not produced. Therefore, the distortion produced at the time of small signals can be made smaller.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、ディジタルオーディオ等の連続したアナロ
グ量を再生するディジタル/アナログ変換(以下D ’
/ A変換という)装置に関するものである。
[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to digital/analog conversion (hereinafter referred to as D'
/ A conversion) device.

〔従来の技術〕[Conventional technology]

ディジタルオーディオ再生装置で使用されているD/A
変換器には多くの種類があるが、最も一般的なものは、
第2図に示すような、電流値がi。
D/A used in digital audio playback equipment
There are many types of converters, but the most common ones are
As shown in FIG. 2, the current value is i.

1/2i、]/4i   1/2”−”iであるn個の
電流源10ILp 10h、−I Qnと、それぞれに
対応するスイッチlla、llb  ・・11nとスイ
ッチドライバ12a、12b・・・ 12nで構成され
ている。
1/2i, ]/4i 1/2"-"i, n current sources 10ILp 10h, -I Qn, corresponding switches lla, llb...11n, and switch drivers 12a, 12b... 12n It is made up of.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第2図の構成をした従来のD/A変換器は、各電流源の
精度、各スイッチの特性差等により、全ピットが反転す
るバイポーラゼロでの誤差を小さくするのが困難で、特
に調整を設けない場合は、ここで最大の誤差を生ずる。
In the conventional D/A converter with the configuration shown in Figure 2, it is difficult to reduce the error at bipolar zero, where all pits are reversed, due to the accuracy of each current source, the characteristic difference between each switch, etc., and it is especially difficult to make adjustments. If not provided, the largest error will occur here.

ディジタルオーディオ再生装置ではほとんどの場合、こ
のパイポーラゼ四点を信号ゼロ点として使用するため、
第3図に示すようにゼロクロス歪みを生じ、特に小信号
の時の歪みが大きくなるなどの問題点があった。
Most digital audio playback devices use these four bipolar points as signal zero points, so
As shown in FIG. 3, zero-crossing distortion occurs, and the distortion becomes particularly large when the signal is small.

この発明は、上記のような問題点を解消するためになさ
れたもので、高い精度を要求せず(こ、小信号時の歪み
を小さくできるI) / A変換装置を得ることを目的
とする。
This invention was made to solve the above-mentioned problems, and aims to provide an I/A converter that does not require high accuracy (i.e., can reduce distortion at the time of small signals). .

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係わるD / A変換装置は、ディジタル演
算による定数乗算器と定数加算器と、ディジタル/アナ
ログ変換器と、バンドパスフィルタとから構成したもの
である。
The D/A converter according to the present invention is composed of a constant multiplier and a constant adder using digital operations, a digital/analog converter, and a bandpass filter.

〔作用〕[Effect]

この発明におけるD/A変換器のバイポーラゼロ点は、
定数加算器によるオフセットのために、信号のゼロ点と
一致せず、このオフセット以下の信号では、バイポーラ
ゼロ点で発生する歪みの影響を受けない。
The bipolar zero point of the D/A converter in this invention is
Due to the offset by the constant adder, it does not coincide with the zero point of the signal, and signals below this offset are not affected by the distortion that occurs at the bipolar zero point.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図において、2ば入力したディジタル信号に定数K
を乗算する定数乗算器、3ば定数乗算器2の出力に定数
りを加算する定数加算器、4はD/A変換器、5は再生
アナログ信号帯域外成分を除去するトバンドパスフィル
タ(以下BPFという)、6は再生アナログ信号を出力
する出力端子である。
In Figure 1, a constant K is applied to the input digital signal.
3 is a constant adder that adds a constant to the output of constant multiplier 2, 4 is a D/A converter, and 5 is a bandpass filter (hereinafter referred to as 6 is an output terminal for outputting a reproduced analog signal.

次に動作について説明する。入力端子1より入力したデ
ィジタル信号に、定数乗算器2で定数Kを掛は定数加算
器3でディジタル信号にDCオフセット(定数L)を加
えろ。この時、D/A変換器4のピーク値を越えると、
D/A変換後の信号の極性が反転するため、定数は以下
の式を満足する様に選ぶ。
Next, the operation will be explained. Multiply the digital signal input from input terminal 1 by a constant K in constant multiplier 2, and add a DC offset (constant L) to the digital signal in constant adder 3. At this time, if the peak value of the D/A converter 4 is exceeded,
Since the polarity of the signal after D/A conversion is reversed, constants are selected to satisfy the following equation.

(D/A変換器4のピーク値)x(1−K)≧L定数加
算N3の出力をD/A変換N4でD/A変換するが、乙
のディジタル信号はオフセットを持つため、第2図に示
すように、オフセット以下の信号はD/A変換器のバイ
ポーラゼロ点をクロスしないため第4図のような大きな
歪みを生じない。
(Peak value of D/A converter 4) As shown in the figure, since the signal below the offset does not cross the bipolar zero point of the D/A converter, it does not cause large distortion as shown in FIG.

D/A変換器4の出力をBPF5で不要帯域成分を取り
除くと、定数加算N2で加算されたDCオフセットは除
去されたアナログ信号が出力端子6に出力される。
When unnecessary band components are removed from the output of the D/A converter 4 by the BPF 5, an analog signal from which the DC offset added by the constant addition N2 has been removed is output to the output terminal 6.

また、バイポーラゼロ点をクロスする信号レベルでは、
歪みの発生に関してオフセットを加える事による変化が
小さい。
Also, at the signal level that crosses the bipolar zero point,
The change in distortion caused by adding an offset is small.

〔発明の効果〕〔Effect of the invention〕

以上のように、乙の発明によれば、小信号時はD/A変
換器の゛バイポーラゼロ点をクロスしないので、高い精
度のD/A変換器を用いなくとも歪みの小さいアナログ
信号を得られる効果がある。
As described above, according to the invention of B, when the signal is small, it does not cross the bipolar zero point of the D/A converter, so an analog signal with low distortion can be obtained without using a high precision D/A converter. It has the effect of

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例によるD/A変換装置を示
すブロック図、第2図はこの発明によるD/A変換出力
波形を示す図、第3図は従来のD/A変換装置の回路構
成図、第4図はその出力波形を示す図である。 図において、2は定数乗算器、3は定数加算器、4はD
/A変換器、5はバンドパスフィルタである。 代理人 大 岩 増 雄(外2名) 升1 図 4:”/A褒減番 5: パンY”ハ0又フΔルタ 牙2図
FIG. 1 is a block diagram showing a D/A converter according to an embodiment of the present invention, FIG. 2 is a diagram showing a D/A conversion output waveform according to the present invention, and FIG. 3 is a diagram showing a conventional D/A converter. The circuit configuration diagram, FIG. 4, is a diagram showing the output waveform. In the figure, 2 is a constant multiplier, 3 is a constant adder, and 4 is D
/A converter, 5 is a band pass filter. Agent Masuo Oiwa (2 others) 1 square Figure 4: "/A reward number 5: Pan Y" 0 Matata Furuta Fang 2 Figures

Claims (1)

【特許請求の範囲】[Claims] ディジタル演算による定数乗算器および定数加算器と、
ディジタル/アナログ変換器と、バンドパスフィルタか
ら構成したことを特徴とするディジタル/アナログ変換
装置。
A constant multiplier and a constant adder using digital operations;
A digital/analog conversion device comprising a digital/analog converter and a bandpass filter.
JP13090187A 1987-05-27 1987-05-27 Digital/analog converter Pending JPS63294130A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13090187A JPS63294130A (en) 1987-05-27 1987-05-27 Digital/analog converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13090187A JPS63294130A (en) 1987-05-27 1987-05-27 Digital/analog converter

Publications (1)

Publication Number Publication Date
JPS63294130A true JPS63294130A (en) 1988-11-30

Family

ID=15045369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13090187A Pending JPS63294130A (en) 1987-05-27 1987-05-27 Digital/analog converter

Country Status (1)

Country Link
JP (1) JPS63294130A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0241027A (en) * 1988-07-29 1990-02-09 Onkyo Corp Digital/analog converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0241027A (en) * 1988-07-29 1990-02-09 Onkyo Corp Digital/analog converter

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