JPS63294118A - Digital delay circuit - Google Patents

Abstract

PURPOSE:To make the delaying range of OR signals wider, by dividing the frequency of clocks upon receiving each frequency dividing output signal and counting each divided clock, and then, delaying the OR of counting complete signals with the resolution of the period of the clocks. CONSTITUTION:Input signals 21 are inputted to pre-scalers 2 and 3 which divide the frequency of clocks after their frequency is divided by N and control the frequency dividing starting points of the pre-scalers 2 and 3. Each counter 4 and 5 counts frequency divided clocks whose frequency dividing starting points are controlled and outputs a counting complete signal. Then the OR of counting complete signals of N-pieces counters 4 and 5 is taken at OR gates 6 and 12-14 and OR signals are delayed with the resolution of the clocks by means of shift registers 8-11. Therefore, the delaying range of the OR signals can be made wider.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital delay circuit, and particularly to a digital delay circuit suitable for obtaining a wide delay range and a high-speed, highly accurate delay.

[Conventional technology]

As described in Japanese Patent Laid-Open No. 61-75615, a conventional device converts an input time reference signal input with a time period T into a period N.
means for generating N frequency-divided outputs whose phases are sequentially shifted by T; and a means for receiving one of the N frequency-divided output signals and setting a delay amount as a counter input value at the timing of the signal. It consists of N counters whose maximum counting time is NT, and an OR circuit that obtains the OR of the carry signals of the N counters.

A variable delay width from 0 to NT is obtained for the time period T of the input time reference signal.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration the variation in the propagation delay time from the clock of the N counters to the carry signal C8, and the output time reference signal is caused by the variation in the propagation delay time of the N counters. There is a problem that jitter occurs. Furthermore, since the clock is directly input to the preset counter, no consideration is given to the clock frequency, and there is a problem in that the delay resolution is limited by the upper limit of the operating frequency of the counter.

The purpose of the present invention is to provide a system with a wide delay range and high delay resolution.
An object of the present invention is to provide a digital delay circuit that can provide a jitter-free delayed output.

[Means for solving problems]

The above purpose is to receive an input signal and calculate N of the period T of the input signal.
means for generating N frequency-divided outputs in which the double period is shifted by T; N grid-scraper means for receiving each frequency-divided output signal and dividing the clock; and N for counting each frequency-divided clock.
This is achieved by providing N counters, an OR gate that takes the logical sum of the counting end signals of these N counters, and means for delaying the output signal of the OR gate with a resolution of a clock cycle.

[Effect]

The input signal is frequency-divided by N and then input to the respective clock dividers to control the frequency division start point of each clock. Each counter counts the divided clock whose frequency division start point is controlled, and outputs a counting end signal. The count end signals of the N counters are logically summed by an OR gate, and the logically sum signal is delayed by the clock resolution by a final means.

〔Example〕

Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital delay circuit according to an embodiment of the present invention. The digital delay circuit shown in FIG. 1 consists of a divide-by-2 circuit 1 that divides the frequency of an input signal, grease collectors 2 and 3 that can control the starting point of frequency division of a clock based on the output of the divide-by-2 circuit 1, and grease collectors 2 and 3. , 3, an OR gate 6 which takes the logical sum of the counting end signals of the counters 4.5, a demultiplexer 7 controlled by the delay amount input 20, and a continuation circuit which functions as a shift register. Connected D flip-flops 8-11 and O
It is composed of R gates 12 to 14.

Next, the operation of the digital delay circuit configured as described above will be explained in a second manner.
This will be explained using the timing chart shown in the figure. In this embodiment, the explanation will be given assuming that the frequency division number of the grease scrubbers 2 and 3 is 4, and the delay amount in the operation timing chart of FIG. 2 is 15 clocks.

When the input signal 21 is input to the divide-by-2 circuit 1, the divide-by-2 circuit 1 outputs divide-by-2 signals 22 and 24. After receiving the frequency-divided-by-2 signal 22, the grease scaler 2 outputs a frequency-divided clock 23 with a controlled frequency division start point. The divided-by-2 signal 22 and the divided-by-4 clock 23 are input to the counter 4, and the divided-by-2 signal 22 is input to the divided-by-4 clock 23 when the divided-by-2 signal 22 is at the "L" level.
A delay amount of 20 is input at the rising edge of the clock, and the frequency is divided by 4.
It counts only the entered value, that is, three, and outputs a counting end signal 26. On the other hand, grease cracker 3 and counter 5
operates similarly and outputs a counting end signal 27. The counting end signals 26 and 27 are logically summed by the OR gate 6 and input to the enable input EK of the demultiplexer 7. The demultiplexer 7 outputs the counting end signal 28 inputted to the enable human power E from the output terminal Z3 selected in advance by the delay amount 20. Each output of the demultiplexer 7 is inputted via the OR gates 12 to 14 to the D flip-flops 8 to 11 operated by the clock 30, each having a different number of stages through which it passes.
The counting end signal 28 delayed with a resolution of an integral multiple of 4 clock cycles is further delayed with a resolution of 300 clock cycles to obtain a delayed signal 29.

As explained above, according to this embodiment, by providing a grease cracker at the front stage of the counter that performs the delay and a shift register that delays at the clock resolution at the rear stage, there is no restriction due to the operating frequency of the counter. The clock frequency can be increased, and the delay resolution can be improved.

Furthermore, the counting end signals of the two counters provided to expand the variable delay range are logically summed and then cycled by the clock by the D flip-flop, so the propagation delay time between the counters is Jitter in the delayed signal due to variations is removed.

Similarly, in this embodiment, two sets of grease scrubbers and counters are provided, but in order to expand the setting range, it is necessary to increase the number of sets of grease scrubbers and counters and set the frequency division number of the frequency divider circuit that divides the input signal. Just match the numbers. Changing the number of sets does not impair the essence of the present invention. Further, although the explanation has been made assuming that the frequency division number of the prescaler that divides the clock is 4, the present invention is not limited to this. If the frequency division number of the prescaler is set to a larger value, the delay is performed by the clock cycle. It is sufficient to increase the number of connected D flip-flops and the number of outputs of the demultiplexer.

〔Effect of the invention〕

According to the present invention, it is possible to widen the delay range and obtain a delay output with high resolution without jitter.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a digital delay circuit according to an embodiment of the present invention, and FIG. 2 is an operation timing chart of the digital delay circuit shown in FIG. 1...2 frequency divider circuit, 2.3... prescaler, 4,5
...Counter, 6.12-14...OR gate, 7
...Demultiplexer, 8-11...D flip-flop.

Claims (1)

[Claims] 1. Means for receiving an input signal and generating N frequency-divided outputs in which the period N times the period T of the input signal is shifted by T, and N devices for receiving each frequency-divided output signal and dividing the clock frequency. and the means of
N counters that count each divided clock, an OR gate that takes the logical sum of the counting end signals of these N counters, and means for delaying the output signal of the OR gate with the resolution of the clock period. A digital delay circuit.