JPS63294108A - Operational amplifier - Google Patents

Abstract

PURPOSE:To drive a large load with a small idling current against a high differential input voltage, by providing bias circuits and current sources and supplying idling currents to differential input circuits. CONSTITUTION:Prescribed idling currents are supplied to 1st and 2nd current amplifier circuits by means of bias circuits 20-23 and 26-29 and constant- current sources 24 and 25. Then output current of prescribed magnifications are produced from the 1st and 2nd current amplifier circuits in accordance with differential input and the output currents are amplified by current mirror amplifiers 6 and 7 respectively connected with the current amplifier circuits and, as a result, output voltages corresponding to the amplification are produced across output terminals. Therefore, a large load driving capacity can be exerted with a small consuming current against large differential input.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an operational amplifier having a class AB amplification function, which is capable of producing a large load driving capacity for large differential inputs with particularly low current consumption. Regarding operational amplifiers.

[Conventional technology]

As a conventional operational amplifier, there is one shown in FIG. In this operational amplifier, the gates of a P-channel insulated gate FET 2 and an N-channel insulated gate FET 3 are connected to an input terminal 1, and the sources of these FETs are connected to an N-channel insulated gate FET 4 and a P-channel insulated gate FET 1-.
The source of type FET5 is sashed to LJ. Drain of N-channel insulated gate type FET4 and power supply VDD
A current mirror amplifier 6 is connected between the P-channel insulated gate I type FET 5 and the power supply VSS.

Bias voltages V1, 1 and VB2 are applied to the gates of FETs 4 and 5, respectively.

The current mirror amplifier 6 consists of P-channel insulated gate FETs 8, 9 and 10, and the current mirror amplifier 7 consists of N-channel insulated gate FETs II, 12 and 1.
Consists of 3. The drains of FETs 10 and 12 are common and become the output terminal 15 that outputs the output voltage VD, and this terminal 1
A capacitor 14 (CL) is connected between 5 and ground.

In the above configuration, the idling current is determined by the bias VBI and FET4.3 when the input VIN is grounded, and the bias VB□, FET4.3 determines the idling current.
ET2.5 determines the current of these FETs. These currents are amplified by current mirror amplifier 6 and current mirror amplifier 7, respectively. When an input signal is input, a large current can be drawn or sourced at the output depending on the magnitude of the input signal. For example, when a positive input signal is input, FETs 2 and 5 have Vcsz + l Vcss l =V+N+l
VB21---(1,1 (However, ■6,2 and VGSS are the gate of FET2.
Source-to-source voltage) causes a current larger than the idling current to flow. Also, for FET4 and 3, VCS4 +l VCS3 l = VIN+ l
VBI 1 (V6, 4 and VCS:+ are F
A current smaller than the idling current flows due to the gate-source voltage of ET4 and ET3.

The current flowing from FET 4 to 5 is amplified by current mirror circuits 6 and 7, and a current greater than the idling current is sucked from output terminal 15. Further, for example, when a negative input signal 1N is input, a current higher than the idling current can be similarly discharged from the output. The circuit shown in FIG. 3 thus constitutes a so-called class AB amplifier.

[Problem that the invention seeks to solve]

However, conventional operational amplifiers have a problem in that they operate only as an inverting amplifier for an input signal voltage with respect to a grounded input, and cannot take the differential input configuration widely used in operational amplifiers.

[Means for solving problems]

The present invention has been made in view of the above, and in order to be able to have a differential input function in addition to the class AB amplification function, a bias circuit is provided in the input stage, and a current is applied to each of the output sides of the bias circuit. An operational amplifier is provided that regulates the idling current of a differential amplifier circuit by providing a source.

That is, the operational amplifier of the present invention includes the following means.

(1) The bias circuit source (or emitter) is connected to the source (or emitter) of the different polarity amplification element (
The gate (or base) and drain (or emitter) of this amplification element are commonly connected, and this serves as the current source output terminal. These amplifying elements can be insulated gate FETs or bipolar transistors.

(2) The gates and drains of the first and second current source bias circuits are connected between each of the commonly connected amplifying elements and the ground, and a constant current of I12 is caused to flow.

(3) The input terminals of the input-side amplifying element are connected across each other to the output terminals of the bias circuit of the first and second current amplifier circuits.A predetermined idling current is applied to each of the output terminals of the bias circuit, and a predetermined idling current is applied. Outputs the output current.

(4) Current mirror amplifier Connected to the first and second current amplification circuits, the current mirror amplifier is configured to flow a current n times the output current to the output side.

[Effect]

With the above configuration, a predetermined idling current is supplied to the first and second current amplification circuits by the bias circuit and constant current source! Can be tested. The first and second current amplification circuits generate output currents of a predetermined magnification according to the differential input, and the current is further amplified by a current mirror amplifier connected to each current amplification circuit, and an output according to this amplification is generated. Generates voltage at the output terminal.

〔Example〕 Examples of the present invention will be described in detail below.

FIG. 1 is a circuit diagram showing an operational amplifier, in which each gate 1- of N-channel insulated gate type FETs 20 and 21 is connected to input terminal 1, and the drain of each FET is connected to a voltage B V D.
11.

The sources of P-channel insulated gate FETs 22 and 23 are connected to the sources of FETs 20 and 21, respectively.
The drain of FET22 is not shown in FIG. 3 and is connected to the drain of FETII.

On the other hand, the gate of FET 23 is connected to its drain and also to a current source 24 (I,). Further, a current source 25 (T2) is provided, and this current source 25 has an FET2
The gate of FET 2 and the gate and drain of FET 26 are connected.

The source and drain of an N-channel insulated gate type FET 27 are connected between the drain of the FET 26 and the power supply VDD, and a voltage VH is applied to the gate.

N-channel insulated gate type F for gate I of FET27
The gate of ET28 is connected, and its drain is connected to current mirror amplifier 6. Further, the source of the FET 28 is connected to the drain of a P-channel insulated gate type FET 29, which is grounded and whose gate is connected to the gate of the FET 23.

In the above configuration, the idling current in the state of zero differential input voltage is determined as follows. First, FET2
The current of technique 0 and 22 is the current of current source 25 ■2
flows through FETs 27 and 26, thereby generating gate-source voltages of FETs 26 and 27. Vertical versus horizontal W/L of transistors FET20 and 27, FET22 and 26
Assuming that the ratio of is the same and its value is m, the current ■1 flowing through FETs 20 and 22 as shown in the formula below is I + = m I z −−−−−−−(3
). Similarly, if the W/1 ratios of FETs 28 and 21 and I"ETs 29 and 23 are the same, m, then the FETs
The current IN flowing through 28 and 29 is I N ''-m I + ---1--(
4). Now, when I+=Iz and the input/output current ratio of the current mirror circuit is n, the output stage output stage output current 11-6 is expressed by ■Kasumi-n m I, -・----(5) Ru.

Next, the current with respect to the differential input voltage VID will be explained.

V ID = V N V I
(6), the current I'9 flowing through FETs 28 and 29
is the storage 1 of FET21.23 (匈+/b), (Hz/
1z) Then, the current 11 flowing through FETs 20 and 22 is (for ■1-■2). Here, μ. , μ, is the mobility, and COX is the capacitance of the gate oxide film. In the region where FE'r20 and 22 or FET2B and 29 do not turn off to 1, n times the amount flows to the current mirror output, the output power supply I. is subtracted, and Io = nm (1,'-I+') flows from the output terminal. FET20 and 22 or FET2
In the region where one of B and 29 is cut off, the output current I.

The maximum value of the value of is limited by the idling current <1vIDI and becomes aυ. −n m T + , and the output current can take a value equal to the idling current. Furthermore, IVID
When I is increased, 1Iol>nmI, and a current higher than the idling current can flow, so-called AB
make class movements.

Therefore, when a large differential input is input and the output needs to swing greatly, a large output current can be obtained, so phase correction,
The no-load capacity C1 can be charged faster than a class A amplifier. Therefore, the overall centering time can be shortened. Furthermore, this configuration allows a differential input configuration widely used in operational amplifiers to be adopted.

FIG. 2 shows another embodiment of the present invention, in which a PNP transistor and an N P N l-transistor are used in place of the P-channel insulated gate FET and the N-channel insulated gate FET. , the circuit configuration is exactly the same as that of the previous embodiment, and therefore the operation is also the same, so redundant explanation will be omitted. In addition, the transistor Q
, 1-Q14 correspond to each of FET1 T8-13 and 20-29 shown in FIG. 1 as follows.

〔Effect of the invention〕

As explained above, according to the present invention, a bias circuit and a current source are provided to give an idling current to the differential input circuit, so a small idling current can drive a large load even with a large differential input voltage. It is possible to provide an operational amplifier with differential power.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the invention, FIG. 2 is a circuit diagram of another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional operational amplifier. Explanation of symbols 6.7---Current mirror amplifier 20.2
1.27.28 - N-channel insulated gate FET2
2.23.26.29

Claims (1)

[Scope of Claims] A bias circuit having a differential configuration of a pair of amplification element groups to which different input signals are applied, and first and second current sources connected in series to each of the amplification element groups. first and second current amplification circuits that are symmetrically connected to the connection points of the amplifier element group and each of the amplification element groups and perform current amplification according to the differential input; and a pair of current mirror amplifiers that amplify the current at the output terminal according to the level of the input signal.