JP3325707B2 - Operational amplifier - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an operational amplifier whose common-mode signal level can operate from a positive power supply voltage to a negative power supply voltage.

[0002]

2. Description of the Related Art Operational amplifiers are widely used in analog circuits, and the performance of operational amplifiers is so important that the performance of operational amplifiers dominate the performance of analog circuits. In recent years, electronic devices have been miniaturized, and at the same time, analog circuits have been required to operate at a low voltage on the assumption that batteries are used. When the analog circuit is operated at a low voltage, the signal level that can be processed has to be reduced, causing a problem that the S / N characteristic is impaired. Therefore, in order to keep the signal processing voltage range as wide as possible for the operational amplifier, it is preferable that the in-phase input signal level is as wide as possible. If the in-phase input signal range can operate up to the positive and negative power supplies, It can be said that it is the most preferable. However, in the conventional amplifier, such an operational amplifier is difficult to design, and a preferable amplifier cannot be provided.

FIG. 4 shows an example of a conventional operational amplifier having a large common-mode input signal range. Where 131 is the NMO
A first differential amplifying unit having an SFET as an input transistor,
Reference numeral 32 denotes a second differential amplifying unit using a PMOSFET as an input transistor, and 133 denotes a signal synthesizing circuit which synthesizes the signals of the first differential amplifying unit 131 and the second differential amplifying unit 132 to obtain a sum. According to the conventional circuit shown in FIG. 4, when the in-phase input signal is near V _DD , the NMOSFET is connected to the input MOSFET.
The first differential amplifying section 131 which is set to T operates. When the common mode input signal is near V _SS , the PMOSFET
The second differential amplifying section 132, which is an OSFET, operates, and further near the middle between V _SS and V _DD , the first differential amplifying section 1
31 and the second differential amplifier 132 operate. Therefore, the conventional operational amplifier shown in FIG. 4 can operate over all in-phase signals.

[0004]

For this operational amplifier, it is necessary to design two types of first and second differential amplifiers 131 and 132. Therefore, there is a problem that it takes time to design.

[0005] Further, when forming the output part as in the conventional circuit shown in FIG. 4, near VDD-phase input signal as shown in FIG. 5, near the center, when the divided and near VSS, near VDD Then, the F of the second differential amplifier 132
The ET pair is cut off and the first differential increase near VSS
The FET pair of the width unit 131 is cut off. This means
When both input signals are near VDD, I2 is all FE
Will flow out of the T149 and 148 sources,
When both input signals are near VSS, I1 is all
It will flow into the sources of FETs 147 and 148.
Therefore, if both in-phase input signals are near VDD ,
If the value of the current flowing through the load MOSFET151 and 152 if the there becomes I3 -I2, near the center I3
, VSS and I3 + I1, and the load MOSFETs 151 and 152
The fluctuation of the value of the current flowing through becomes large. Where I1 and I
The current values of 2 are assumed to be equal. Therefore, in-phase
If both force signals are near the center, I1 will be differentially increased.
I2 flows to the differential amplifier 132,
Only its own current I3 flows through the signal synthesis circuit 133.
Will be. For this reason, the output operating point fluctuates according to the amount of current flowing through the load MOSFET as shown in FIG. 5 depending on the in-phase input level, resulting in a problem that distortion occurs in the input / output characteristics.

Further, the current flowing through the cascode MOSFETs 147 and 148 fluctuates with respect to the common-mode input signal level. Ie, times to synthesize enter the differential output current
Current flowing through the cascode MOSFET 147 of the
And the current flowing through the cascode MOSFET 148 is completely
Even if the input signals do not have the same level difference,
It changes according to the input DC level. Because of this, the pole position of the transfer function in the operational amplifier fluctuates with respect to the in-phase signal level, so that the current value and the speed are limited due to the design for maintaining the phase margin.

Further, as another conventional example, M. D. PAR
IEEE JOURNA described by DOEN et al.
L OF SOLID STATE CIRCUITS
VOL. 25, NO. 2, there is a circuit example of an APRIL 1990 rail operational amplifier. However, this circuit
Although the distortion is slightly improved by avoiding sudden turning off of the input MOSFET pair of the differential amplification unit, the problem is not essentially solved.

An object of the present invention is to provide an operational amplifier having a large common mode input signal range and excellent linearity performance.

[0009]

In order to achieve the above object, according to the present invention, there is provided an operational amplifier using a MOSFET, wherein a differential input terminal for inputting a differential input and the differential input terminal are provided. A first pair of MOSFETs to which respective signals from the terminals are input, a first differential amplifier circuit having a first current source circuit coupled to a connection point of each source of the pair of MOSFETs, And a second MOSFET pair having the same polarity as the first MOSFET of the first differential amplifier circuit.
An FET pair and a second current source circuit coupled to a connection point of each source of the second MOSFET pair, and outputting a current value flowing through the second current source circuit or the second MOSFET. A current value output circuit configured to detect a value of a current value flowing through a first current source circuit of the first differential amplifier circuit; and a current value output circuit coupled to the current value output circuit. A current subtraction circuit for subtracting the current value output from the predetermined current value from the predetermined current value and outputting the subtracted current value, a third MOSFET pair to which respective signals are input from the differential input terminals, A second differential amplifier circuit comprising: a third current source circuit coupled to a connection point of each pair of sources, the current source circuit comprising a mirror circuit controlled by an output of the current subtraction circuit. And the first First MOSFET dynamic amplifier
A pair and a third MOSFET of the second differential amplifier circuit
MOSF for outputting the same polarity output signal of each of the pair
The drain of the ET is coupled, and includes a load current source connected to a connection point of the drain, and a signal output circuit that inputs and outputs a differential output from the drain connection point, and the differential input terminal In a region of the input signal in which the value of the current flowing through the current source circuit of the first differential amplifier circuit decreases from a predetermined current value or becomes zero according to the input signal supplied to the first differential amplifier circuit, the current subtraction is performed. The current of the current source circuit of the second differential amplifier circuit is controlled so as to increase or to a predetermined current by the circuit output, whereby the first differential amplifier circuit and the second differential amplifier circuit are controlled. The switching operation is performed while overlapping the amplification operations of the differential amplifier circuits, and the second differential amplifier is easily operated when its current source circuit is controlled to have a predetermined set current. An operational amplifier, characterized by an amplifying operation that defines fit.

According to a second aspect of the present invention, there is provided the operational amplifier according to the first aspect, wherein M
MOSF forming a second differential amplifier circuit with an OSFET pair
MOSFETs used for the ET pair have the same polarity,
Each signal from the differential input terminal is supplied to an input MOSFET of a second differential amplifier circuit via a level shifter circuit.
It is characterized in that it is inputted to a pair of gates.

According to a third aspect of the present invention, there is provided the operational amplifier according to the first aspect, wherein the MOS comprises a second differential amplifier circuit.
The MOSFET of the FET pair has the same polarity as the MOSFET used for the MOSFET pair forming the first differential amplifier circuit, and the MOSFET of the second differential amplifier circuit
The paired MOSFETs are depletion-type MOSFETs.

According to a fourth aspect of the present invention, in an operational amplifier using MOSFETs, a differential input terminal for inputting a differential input, a first MOSFET pair for inputting respective signals from the differential input terminal, and A first current source circuit coupled to a connection point of each source of a MOSFET pair, the first MOS transistor
A first differential amplifier circuit having a load current source connected to each drain of the FET pair; and a second MOSFET pair receiving respective signals from the differential input terminals, the first differential amplifier circuit comprising: A second MOSFET pair having the same polarity as the first MOSFET of the dynamic amplifier circuit, and a second current source circuit coupled to a connection point between the respective sources of the second MOSFET pair. Alternatively, a current value output circuit configured to detect a magnitude of a current value flowing to a first current source circuit of the first differential amplifier circuit by outputting a current value flowing to the second MOSFET. A current subtraction circuit coupled to the current value output circuit, subtracting a current value output from the current value output circuit from a predetermined current value, and outputting the subtracted current value; and Input each signal Was a MOSFET pair, said first MOSFET pair of MOSFET constituting the differential amplifier circuit
And a third MOSFET having a polarity different from the polarity of the third MOSFET.
A third current source circuit coupled to a connection point of each source of the FET pair, a current source circuit including a mirror circuit controlled by an output of the current subtraction circuit, and the third MOSFET;
A load current source connected to each drain of T.
And a signal combining circuit that receives and combines the differential outputs of the first differential amplifier circuit and the second differential amplifier circuit and outputs a combined output signal, According to the input signal supplied to the differential input terminal, the current value flowing through the current source circuit of the first differential amplifier circuit decreases from a predetermined current value or becomes zero in an input signal region. The current of the current source circuit of the second differential amplifier circuit is controlled so as to increase by the output of the current subtraction circuit or to become a predetermined set current. The switching is performed while overlapping the amplification operation of the circuit and the second differential amplifier circuit, and the second differential amplifier is controlled when the current source circuit is controlled to have a predetermined set current. Predetermined An operational amplifier, characterized by an amplifying operation.

[0013]

The operational amplifier of the present invention has a positive power supply VDD.Potential of
Input signalOperating differential amplifierAnd the negative power supply V
Differential amplifier that operates even with the SS potential input signalHave
AndMeasure the current flowing through one differential amplifierCurrent measurement
Circuit and, Subtracts the measured current from the specified current value and subtracts
Output current valueCurrent subtraction circuitAnd this current
A mirror circuit controlled by the output current of the subtraction circuit is provided.
This mirror circuit is used as a current source for the other differential amplifier.
By thatThese two differential amplifiersOf the current sources
ControlOnly one of them worksTo letI
ing. Operation shifts from one differential amplifier to the other
When you do it, do not turn it on and off
whileI.e. the narrow DC level range of the input signalBut fixed
The current source gradually decreases from the original current value to zero.
The other gradually increases from zero to reach the original current value.
I do. In this process,These current valuesIe decrease
Current and increasing currentIs always constant
You. This results in the output of each differential amplifier.
To the sum of the force currents,Signal output circuit orFaith
No. synthesis circuitTotal differential input current supplied to the input
Is, Even if the operation shifts from one to the other differential amplifierConstant
Kept inBecause, in-phaseInputsignalchange ofAgainstWorking power
The flow is not subject to any change, and thereforeOutput voltageAlsoAll change
Not accept,furtherVery linear performance in input / output characteristics
An excellent operational amplifier can be provided.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a commonly used first differential amplifier comprising input MOSFETs 10 and 11 and a constant current source 14;
Is connected to an input terminal pair of a differential amplifier having the same configuration as the first differential amplifier 1 and output terminals of level shifters 6 and 7 having a source follower configuration, and an input signal is differentially transmitted through the level shifters 6 and 7. A second differential amplifying unit transmitted to input MOSFETs 19 and 20 of the amplifying unit. Reference numeral 3 denotes an input of a signal current from the first and second differential amplifying units 1 and 2.
This is a signal output circuit that outputs to an output terminal . 4 is the current measurement
The input MOSFET 1 of the first differential amplifier 1 is a constant circuit.
Differences having exactly the same configuration as 0 and 11 and the constant current source 14
Includes dynamic amplifier. However, the load MOSFET corresponding to the load MOSFET pair (current source) of the first differential amplifying unit.
ET pairs 32 and 33 are provided, except that these gates and drains are not connected. In other words, 4
The input MOSFETs 30 and 31 and the constant current source 34
Exactly the same as power MOSFETs 10 and 11 and constant current source 14
The configuration is exactly the same so that the same operation is performed. 5 is
Load MO of the current measuring circuit 4 from a constant bias current value
A current subtraction circuit that can obtain a current value obtained by subtracting a current value flowing through the SFET pairs 32 and 33. The current value obtained from the current subtraction circuit 5, the input MOSFET 19 of the second differential amplifier 2 and The value of the current flowing through 20 is the same.

The operation of the embodiment of the present invention shown in FIG. 1 will be described. First, when the in-phase input signal is near the middle between VDD and VSS, the first differential amplifier 1 operates normally.
At this time, in the current measuring circuit 4 configured with the same circuit as the first differential amplifier 1 , in other words, the first differential amplifier
In the current measuring circuit 4 configured to perform the same operation as
Oite, the sum of the current flowing through the load MOSFET pairs 32 and 33, since the MOSFET30 and 31 is within the normal operating range, is used as a current source MOSF
The current flowing through the ET34 , that is, the current of the first differential
Flows through the MOSFET 44 used as a current source
Current, equal to. The MOSFET of the current subtraction circuit 5
35 and 36 are MOSFETs 32 of the current measuring circuit 4.
And 33 constitute a current mirror circuit,
The sum of the currents flowing through SFETs 35 and 36 is also
It becomes equal to the current flowing through the SFET 34. In the current subtraction circuit 5, the current flowing through the MOSFET 38 is MOSF
MOSFETs 35 and 36 are derived from the current flowing through ET37.
Is the value obtained by subtracting the current flowing through Since the bias voltage applied to the bias terminals B1 and B2 is adjusted to make the current flowing through the MOSFET 37 of the current subtraction circuit 5 the same as the current flowing through the MOSFET 34 of the current measurement circuit 4,
No current flows through the MOSFET 38 and the MOSFET
MOSFE which is a current mirror circuit for T38
No current flows to T39. As a result, MOSFE
MOSFET used as a current source of T40 and the second differential amplifier 2 serving as a current mirror circuit with T40
No current flows through the second differential amplifier 23, and the second differential amplifier 2 does not operate.

Next, a case where the in-phase input signal is near V _DD will be described. When the in-phase input signal is near V _DD , the MOSFET as the input element of the first differential amplifier 1
Bias terminal B so that 10 and 11 enter the saturation region
By adjusting the bias voltage applied to ₃ , the first differential amplifier 1 operates normally. Therefore, the second differential amplifying unit 2 does not operate as in the case where the above-mentioned in-phase input signal is near the middle between V _DD and V _SS .

A case where the common mode input signal is near VSS will be described. When the common mode input signal is near VSS,
The MOSFETs 10 and 11, which are the input elements of the first differential amplifier 1, are turned off because a sufficient gate-source voltage cannot be obtained. At this time, in the current measurement circuit 4 which is configured by the same circuit as the first differential amplifier 1 and operates in the same manner , the MOSFETs 30 and 31 are similar to the differential amplifier 1.
To turn off, the sum of the current flowing through the load MOSFET pairs 32 and 33 are made to zero. The MOSFETs 35 and 36 of the current subtraction circuit 5
Since the current mirror circuit is formed with the SFETs 32 and 33, the sum of the currents flowing through the MOSFETs 35 and 36 is also zero, as is the current flowing through the MOSFET 34. In the current subtraction circuit 5, the current flowing through the MOSFET 38 is obtained by dividing the current flowing through the MOSFET 37 into the MOS
The value is obtained by subtracting the current flowing through the FETs 35 and 36.
Since a current determined by the bias voltage applied to the bias terminal B2 flows through the MOSFET 37, as a result, the same current flows through the MOSFET 39 as a current mirror circuit with respect to the MOSFET 38. For this reason, the MOSFET 40 and the MOSF of the second differential amplifying unit 2 serving as a current mirror circuit therewith.
The same current flows through ET23. Here, the input signal is level-shifted to a level at which the MOSFETs 19 and 20 operate normally by the operation of the level shifters 6 and 7 in the second differential amplifier 2, and the second differential amplifier 2 operates during the normal operation. The normal operation is performed in the same manner as the differential amplifier 1.

As described above, the operational amplifier of the present invention operates with the first differential amplifier section which operates even with the input signal of the potential of the positive power supply VDD and the input signal with the potential of the negative power supply VSS.
It has a second differential amplifier , and only one of these two differential amplifiers is operated by the current measuring circuit 4 and the current subtracting circuit 5. Also, when the operation shifts from one to the other differential amplifying unit, the constant current source gradually decreases from the original current value to zero, instead of suddenly turning on and off, but for a short period, The other gradually increases from zero to reach the original current value .
That is, the sum of the decreasing and increasing currents is always kept constant. That is, the load MOSF of the signal output circuit 3
Since the current flowing through the ET24 and 25 is always constant, an input applied to the input 1 and 2, the output voltage will not receive any changes with respect to <br/> signal change in phase, very in input-output characteristics Therefore, an operational amplifier having excellent linear performance can be provided.

Since the currents flowing through the cascade MOSFETs 26 and 27 are also always constant, the pole position of the transfer function caused by the cascade MOSFET does not change with respect to the in-phase input signal. It is also preferable in performing.

[0021] In the embodiment shown in FIG. 1, the differential amplifier portion of the current measuring circuit 4, Ri same der the first differential amplifier 1,
Has been to Rutoshite describe the same operation, in reality, the operational amplifier
In order to save chip size and current consumption,
Only the size of the MOSFET may be reduced at a fixed ratio while the circuit configuration remains the same. Similarly, the current subtraction circuit 5
Current mirror circuit (MOSFETs 35, 36, 3)
9) For the same reason, the current consumption can be reduced by reducing the size at a fixed rate. In addition, since the accuracy of the current mirror circuit is not accurate, the current becomes insufficient due to the mismatch of the current mirror circuit during the transitional period in which the operation is switched from the first differential amplifier 1 to the second differential amplifier 2, so that the current becomes insufficient. In some cases, the operation may not be performed or the operation may be deteriorated. In order to avoid this problem, the current of the MOSFET 37 of the current subtraction circuit 5 may be set to be relatively large so that a small amount of current flows in advance to the second differential amplifier 2 side.

In the embodiment shown in FIG. 1, the level shifter 6
And 7 use a source follower circuit, but any type of input follower such as an emitter follower using a bipolar circuit may be used as long as the input signal can be shifted by a desired amount.

In the embodiment shown in FIG.
Although it has been described as being constituted by FETs, the PMOSF
It is clear that the same effect can be obtained in the case of ET by designing based on the same method.

A configuration without using the level shifters 6 and 7 may be adopted. In the embodiment shown in FIG. 1, a depletion-type NMOSFET is used as an input MOSFET so that operation is possible even when the input of the input MOSFET pair 19 and 20 of the second differential amplifier unit 2 is at V _SS . It is clear that such a configuration operates in the same manner as the embodiment shown in FIG. 1 even without a level shifter.

FIG. 2 shows another embodiment of the present invention. In FIG. 2, reference numeral 41 denotes a normally used first differential amplifier comprising input MOSFETs 50 and 51 and a constant current source 54, and 42 denotes a MOSFET having a polarity different from that of the first differential amplifier 1.
T, PMOSFETs 55 and 56 in this example
Reference numeral 43 denotes a second differential amplifier used as an OSFET, and reference numeral 43 denotes a signal voltage from the first and second differential amplifiers 41 and 42.
This is a signal synthesis circuit that synthesizes the flow . 44, input MOSFETs 50 and 51 of the first differential amplifier 41 and a constant current source
This is a current measurement circuit having the same configuration as that of the current measurement circuit 54 . However
And a load MOSFET pair (current source) of the first differential amplifier section
Bei load MOSFET pairs 72 and 73 correspond to the
For example, except that between these gate and the drain is connected. 45 is a current subtraction circuit for obtaining a current value obtained by subtracting a current value flowing through the load MOSFET pair 75 and 76 of the current measurement circuit from a constant bias current value.
The current value obtained from the current subtraction circuit 45 and the current value flowing through the input MOSFETs 55 and 56 of the second differential amplifier 42 are used in the same manner.

The operation of the embodiment shown in FIG. 2 will be described. First, when the common mode input signal is near the middle of the V _DD and V _SS are first differential amplifier 41 operates properly. At this time,
In the current measuring circuit 44 configured by the same circuit as the first differential amplifying unit 41, the load MOSFET pairs 72 and 73
Is equal to the current flowing through MOSFET 74 used as a current source since MOSFETs 70 and 71 are within the normal operating range. In the current subtraction circuit 45, since the MOSFETs 75 and 76 constitute a current mirror circuit with the MOSFETs 72 and 73 of the current measurement circuit 44, the MOSFETs 75 and 76
The sum of the currents flowing through the
It becomes equal to the current flowing through ET74. Here, MOSF
The current flowing through the ET 78 has a value obtained by subtracting the current flowing through the MOSFETs 75 and 76 from the current flowing through the MOSFET 77. When the bias voltage applied to the bias terminals B ₁ and B ₂ is adjusted so that the current flowing through the MOSFET 77 and the current flowing through the MOSFET 74 of the current measuring circuit 44 are the same, no current flows through the MOSFET 78.
Therefore, no current flows through the MOSFET 59 of the second differential amplifier 42, which is a current mirror circuit for the MOSFET 78. As a result, the second differential amplifier 42 does not operate.

Next, a case where the in-phase input signal is near V _DD will be described. Even when the common mode input signal is near V _DD, by adjusting the bias voltage is MOSFET50 and 51 is an input device is applied to the bias terminal B ₃ to enter a saturation region, a first differential amplifier 41 Works fine. Therefore, the second differential amplifier 42 does not operate as before.

The case where the common mode input signal is near V _SS will be described. When the common mode input signal is near V _SS ,
MOSFET 50 as an input element of the first differential amplifier 41
And 51 are turned off because a sufficient gate-source voltage cannot be obtained. At this time, in the current measuring circuit 44 configured the same as the first differential amplifier 41, the load MO
The sum of the currents flowing through the SFET pairs 72 and 73 is
Since the FETs 70 and 71 are turned off similarly to the first differential amplifying unit 41, they become zero. In the current subtraction circuit 45, the MOSFETs 75 and 76 form a current mirror circuit with the MOSFETs 72 and 73.
The sum of the currents flowing through FETs 75 and 76 is also MOSF
It becomes zero similarly to the current flowing through ET74. Where M
The current flowing through the OSFET 78 has a value obtained by subtracting the current flowing through the MOSFETs 75 and 76 from the current flowing through the MOSFET 77. Here, since a current determined by the voltage applied to the bias terminal B2 flows through the MOSFET 77, a current having the same value as the current flowing through the MOSFET 77 also flows through the MOSFET 78. As a result, MOSF
A current having the same value as that of the MOSFET 77 also flows through the MOSFET 59 of the second differential amplifier, which is a current mirror circuit for the ET 78. The second differential amplifying unit 42 has an input MOS
Since the FET is a PMOSFET, it can operate normally even with a signal near V _SS, so that it operates exactly the same as the first differential amplifying unit 41 during normal operation. That is, FIG.
1 can also obtain the same result as FIG.

When the operational amplifier of the present invention is used, an output amplifier circuit may be added as shown in FIG. 3 to further improve the performance of the operational amplifier circuit.

In FIG. 3, reference numeral 123 denotes a first differential amplifier,
124 is a second differential amplifier, 125 is a signal combining circuit for combining the signals of the first and second differential amplifiers 123 and 124, 126 is a current measuring circuit, 127 is a current subtracting circuit, and 128 and 129 are It is a level shifter. The configuration and operation of these circuits are the same as those of the operational amplifier shown in FIG. 118 is an output amplifier circuit,
It is connected to the output of the signal synthesis circuit 125.

The output amplifier circuit 118 is connected to the current source 11
9 and MOSFET 120. In this output amplifying circuit 118, the resistor 121 and the capacitor 122 are inserted to keep a sufficient phase margin. By adding the output amplifier circuit 118, amplification of an output signal and output current capability can be improved.

[0032]

As described above, the operational amplifier of the present invention has two
Comprising a differential amplifier section, the other up differential by the current measuring circuit and the current subtraction circuit in which the same structure as the one of the differential amplifier
Connected to the connection point of each source of the input MOSFET pair
Control the current source circuit
If it deviates from the operation, it can switch to the other operational amplifier.
Possible and therefore acceptable as an operational amplifier
Set the input common-mode signal range from the negative power supply to the positive power supply .
It is possible to provide an operational amplifier Rukoto can become, and the strain has a very low linear characteristics.

Further, since the pole position of the transfer function of the operational amplifier is fixed irrespective of the common-mode input signal range, high-speed circuit design is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an operational amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an operational amplifier according to another embodiment of the present invention.

FIG. 3 is a circuit diagram of an operational amplifier of the present invention to which an output amplifier circuit is added.

FIG. 4 is a circuit diagram of a conventional operational amplifier.

FIG. 5 is a graph showing input / output characteristics of a conventional operational amplifier.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 first differential amplifier 2 first differential amplifier 3 signal output circuit 4 current measuring circuit 5 current subtraction circuit 6, 7 level shifter 41 first differential amplifier 42 second differential amplifier 43 signal combining circuit 44 Current measurement circuit 45 Current subtraction circuit 118 Output amplification circuit 123 First differential amplification section 124 Second differential amplification section 125 Signal output circuit 126 Current measurement circuit 127 Current subtraction circuit 128, 129 Level shifter 131 First differential amplification section 132 second differential amplifier 133 signal combining circuit

Claims (4)

(57) [Claims] 1. An operational amplifier using a MOSFET , comprising: a differential input terminal for inputting a differential input; and a first input terminal for inputting respective signals from the differential input terminal .
Of MOSFET pairs, connection of the source of the MOSFET pairs
A first differential amplifier circuit having a first current source circuit coupled to a point, and a second differential amplifier circuit receiving respective signals from the differential input terminals.
The said a of the MOSFET pair of first differential amplifier circuit
A second MOSFET pair having the same polarity as the first MOSFET;
Coupled to the junction of each source of the second MOSFET pair
A second current source circuit, wherein the second current source circuit
Outputs the current value flowing through the second MOSFET.
And, the flow in the first current source circuit of the first differential amplifier circuit
Out the current value and configured to detect the magnitude of the current value
Power circuit, and coupled to the current value output circuit, from the current value output circuit.
Subtract output current value from predetermined current value
And a current subtraction circuit for outputting a subtracted current value, and a third circuit for receiving each signal from the differential input terminal.
MOSFET pair and connection of each source of the MOSFET pair
A third current source circuit coupled to a point, wherein the current subtraction is
Composed of a mirror circuit controlled by the output of the circuit
A second differential amplifier circuit having a current source circuit; a first MOSFET pair of the first differential amplifier circuit;
That of the third MOSFET pair of the second differential amplifier circuit
MOSFET gates that output output signals of the same polarity
The lanes are connected and connected to the connection point of the drain.
Input and output differential output from the connected load current source and the drain connection point
A signal output circuit, and according to an input signal supplied to the differential input terminal,
The value of the current flowing through the current source circuit of the first differential amplifier circuit is
Decrease from the preset current value or become zero
In the area of the input signal, the output of the current subtraction circuit
The current of the current source circuit of the second differential amplifier circuit increases.
Or a preset current
, Whereby the first differential amplifier circuit and the second differential amplifier circuit
While overlapping the amplification operation of the differential amplifier circuit
Switching, and the second differential amplifier
Control so that the current source circuit has a predetermined set current
An operational amplifier, which performs a predetermined amplification operation when performed . 2. An MO constituting the first differential amplifier circuit
MOSFE forming a second differential amplifier circuit with an SFET pair
MOSFET used in the T pairs are the same polarity, before
Each signal from the differential input terminal is connected to an input MOSFET pair of a second differential amplifier circuit via a level shifter circuit .
The operational amplifier according to claim 1 , wherein the signal is inputted to a gate of the operational amplifier. 3. A MOSF constituting a second differential amplifier circuit
ET pair of MOSFET is a MOSFET and the same polarity to be used in MOSFET pair constituting said first differential amplifier circuit, the second MOSFET of the MOSFET pair of the differential amplifier circuit in the depletion-type MOSFET Ah
The operational amplifier according to claim 1, characterized in that that. 4. An operational amplifier using a MOSFET.
Te, first entered a differential input terminal for inputting a differential input, the respective signals from the differential input terminals
MOSFET pair and connection of each source of the MOSFET pair
A first current source circuit coupled to a point , said first MOSFET
A first differential amplifier circuit having a load current source connected to each drain of the T pair , and a second differential amplifier circuit that receives respective signals from the differential input terminals.
Of the first differential amplifier circuit.
A second MOSFET pair having the same polarity as the first MOSFET;
Coupled to the junction of each source of the second MOSFET pair
A second current source circuit, wherein the second current source circuit
Outputs the current value flowing through the second MOSFET.
Then, the current flows to the first current source circuit of the first differential amplifier circuit.
Current value output configured to detect the magnitude of the current value
Power circuit, and coupled to the current value output circuit, from the current value output circuit.
Subtract output current value from predetermined current value
And a current subtraction circuit for outputting the subtracted current value, and a MO receiving each signal from the differential input terminal.
An MO that constitutes the first differential amplifier circuit with the SFET pair
A third polarity different from the polarity of the MOSFET of the SFET pair
MOSFET and connection point of each source of the MOSFET pair
A third current source circuit coupled to the output of said current subtraction circuit
Current source circuit composed of mirror circuit controlled by
Connected to each drain of the third MOSFET
A second differential amplifier circuit having a load current source; and a second differential amplifier circuit before the first differential amplifier circuit and the second differential amplifier circuit.
The differential output is input and combined, and the combined output signal is output
A signal combining circuit, and according to an input signal supplied to the differential input terminal,
The value of the current flowing through the current source circuit of the first differential amplifier circuit is
Decrease from the preset current value or become zero
In the area of the input signal, the output of the current subtraction circuit
The current of the current source circuit of the second differential amplifier circuit increases.
Or a preset current
, Whereby the first differential amplifier circuit and the second differential amplifier circuit
While overlapping the amplification operation of the differential amplifier circuit
Switching, and the second differential amplifier
Control so that the current source circuit has a predetermined set current
When performing this operation, perform a predetermined amplification operation.
Operational amplifier according to symptoms.