JPS63294033A - Abnormal processor detection system - Google Patents

Abstract

PURPOSE:To fix the detection time and to perform diagnosis even during system operation by successively sending diagnostic information destined for a maintenance operation processor itself onto a bus from this processor and receiving overflow information to discriminate an abnormal processor. CONSTITUTION:When a maintenance operation processor 4 transmits diagnostic information 10 destined for the processor 4 itself, information 10 is circulated once on a common bus 1 and is returned to the processor 4 if there are no abnormal processors. If trouble occurs in a processor 2B, this processor receives information 10 and stores it in a main memory 20. When transmission of diagnostic information 20, 30-is repeated several times, the processor 2B successively receives these information; and overflow occurs when the quantity of these information exceeds the capacity of the memory 20. At this time, the processor 2B transmits overflow information 90 to the processor 4 through the bus 1. When receiving information 90, the processor 4 discriminates the abnormal processor 2B of the transmission source of information 90 by an abnormal processor detecting part 40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an abnormal processor detection method, and more particularly to an abnormal processor detection method in a packet switching system.

[Conventional technology]

Conventionally, in order to detect this type of abnormal processor, one of the multiple 10 processors that performs packet switching control is automatically or manually disconnected from the common bus, and in this state, the maintenance processor connected to the common bus is Diagnose whether the processors disconnected from the common bus are normal by sending diagnostic information from the operating processor to each of the processors in operation and checking whether each processor receives the diagnostic information correctly. However, if the processor is normal, an abnormal processor is detected by sequentially disconnecting the next processor from the common bus and diagnosing it.

[Problem that the invention seeks to solve]

The abnormal processor detection method in the conventional packet switching system described above sequentially searches and diagnoses multiple processors that perform packet switching control one by one, so the search time is short when there are many processors configuring the packet switching system. The disadvantage is that it takes too much time. Furthermore, since the search is performed while separating the processor from the common bus, it has the disadvantage that it cannot be applied to a running system.

[Means for solving problems]

The abnormal processor detection method of the present invention includes a plurality of processors that perform packet i/exchange control, a set of common buses that interconnect these processors, and a maintenance/operation processor that performs maintenance operations on these processors and the common bus. In the packet switching system, each processor has a function of transmitting overflow information to the common bus when it receives information that exceeds the capacity of its own main memory, and the maintenance and operation processor has a function of transmitting overflow information to the common bus. The processor has a function of receiving overflow information from a processor, and receives overflow information from an abnormal processor in which the maintenance operation processor mistakenly receives information addressed to itself that is sent to the common bus one after another and stores it in the main memory. By doing so, the abnormal processor that is the transmission source of the overflow information is identified.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of a multiprocessor-configured packet switching system showing one embodiment of the present invention.

In the figure, the packet switching system includes a set of common buses 1 and processors 2A, 2B, and 2C connected to the common bus 1 and performing packet switching.

2N, and a maintenance and operation processor 4 that maintains and operates these processors and the common bus.

Each processor, for example processor 2B, has main memory 2
0 and a buffer status display table 21, the maintenance/operation processor 4 includes an abnormal processor detection unit 40 that receives overflow information from an abnormal processor and identifies the source thereof.

Next, FIGS. 2(a) and 2(b) are block diagrams showing an example of the main memory and buffer status display table in FIG. 1, and FIGS. 3 and 4 respectively show the information flow and overflow determination in FIG. 1. FIG. 5, which is a diagram showing the flow of processing, is a diagram showing an example of the format of overflow information.

Next, the operation of this embodiment will be described assuming that Bromo Sosa 2B is an abnormal processor that erroneously captures information destined for another processor and stores it in the main memory 20.

As shown in FIG. 3, when the maintenance and operation processor 4 transmits the diagnostic information 10 to itself (step 101), it is originally sent to the processor 2A.

If there is no abnormality in 2B, 2C, ~2N, this diagnostic terminal wR
10 goes around the common bus 1 and returns to the maintenance/operation processor 4, but the processor 2B that is the search target has a fault and receives the diagnostic information 1o by mistake, causing it to be sent to the main memory 2.
It is stored to 0 (step 102). Such diagnostic information 2
0.30. Repeat sending ~ several times (Ste Tsubu 10)
3-Step 106) When the processor 2B receives information that exceeds the capacity of the main memory 20 it owns, the main memory 20 overflows (Step 107). Then, the overflow information 90 is transmitted to the maintenance/operation processor 4 via the common bus 1 (step 108). When the maintenance and operation processor 4 receives this overflow information 90, the abnormal processor detection unit 40 identifies the abnormal processor that is the source of the overflow information 90 (step 109).

Next, an overflow determination method in the abnormal processor 2B will be described with reference to FIG.

The main memory 20 owned by the processor 2B is divided into a size that allows information to be written once, and a buffer status display table 21 is provided corresponding to each divided buffer A, B, C, ~. While this is being written, the buffer A 211 of the corresponding buffer status display table 21 is in use. An overflow is determined when new information is received after all buffer tables are in use.

Next, the overflow determination process will be explained using FIGS. 2 to 4.

When the diagnostic information 10 is received (step 401), first, the CPU 21 searches the buffer status display table 21 for an unused buffer table to see if there is space left to write the diagnostic information 10 in the main memory 20. (step 402). For example, 211 for buffer A
is unused (step 403), buffer 2
11 is in use (step 404) and the buffer A20
Diagnosis information 10 is written to 1 (step 405). If no unused buffer table remains, it is determined that there is an overflow (step 403), and overflow information 90 is sent to the maintenance and operation processor 4 (step 406).

Next, a method of searching for the source of overflow information will be described with reference to FIGS. 1, 3, and 5.

In the maintenance operation processor 4, an abnormal processor detection unit 40
The destination processor number 502 of the overflow information 90 sent is checked, and if it is the own processor number, that is, the number of the maintenance and operation processor 4, the overflow information 90 is received and the information type 503 is checked. If it is determined that this is overflow information, the processor number 501 of the transmission source is checked to identify which processor caused the overflow.

〔Effect of the invention〕

As explained above, the present invention solves an abnormality in which the maintenance and operation processor sends diagnostic information addressed to itself to the common bus one after another, and the information addressed to the maintenance and operation processor is mistakenly received as being addressed to itself and stored in the main memory. The processor receives the diagnostic information and writes information that exceeds the main memory capacity to cause an overflow, and the abnormal processor sends the overflow information to the maintenance and operation processor, which processor is searching for the abnormal processor. Since it is possible to identify whether the packet is the same or not, there is an effect that the detection time is constant regardless of the number of processors that make up the one-packet switching system. Additionally, an abnormal processor can be detected without disconnecting the processor from the common bus.
This has the advantage that it can also be applied to systems in operation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a packet switching system with a multiprocessor configuration showing an embodiment of the present invention, FIG. 2(a),
(b) is a configuration diagram showing an example of the main memory and buffer status display table in FIG. 1; FIGS. 3 and 4 are diagrams showing the flow of information and overflow determination processing in FIG. 1, respectively; The figure shows an example of the format of overflow information. DESCRIPTION OF SYMBOLS 1... Common bus, 2A, 2B, 2C, ~2N... Processor, 4... Maintenance and operation processor, 20... Main memory, 21... Buffer status display table, 40
...Abnormal processor detection unit.・;- Agent Patent Attorney Susumu Uchihara, / 11 Kasumi Perforation 2 (CL”) Part 3 (2) Maintenance and Operation Busse Sotsugyu Odori Basin 1
Tatsumi Fuse b Se Tsubu 2β Figure 4

Claims (1)

[Claims] In a packet switching system consisting of a plurality of processors that perform packet switching control, a set of common buses that interconnect these processors, and a maintenance and operation processor that performs maintenance and operation of these processors and the common bus, each of the above-mentioned The processor has a function of transmitting overflow information to the common bus when it receives information that exceeds the capacity of its own main memory, and the maintenance and operation processor has a function of receiving overflow information from the processor, By receiving overflow information from an abnormal processor in which the maintenance and operation processor mistakenly receives information intended for itself that has been sent one after another to the common bus and stores it in the main memory, the abnormality in the source of the overflow information is detected. An abnormal processor detection method characterized by identifying a processor.