JPH08227406A - Parallel computer - Google Patents

Abstract

PURPOSE: To improve the reliability of a network over which plural processors are connected and perform inter-processor data transfer. CONSTITUTION: The parallel computer consists of arithmetic processors PU(1) 1... PU(n) 2 and a processor PU(n+1) 3 exclusively for diagnosis which include CPUs 11, 21, and 31, memories 12, 22, and 32, network interface circuits 14, 24, and 34 each having a mechanism that uses a diagnostic packet for diagnosing a fault of a process or network and reporting it to an OS and a user and takes a self-test wherein the diagnostic packet is sent and received by itself, a mechanism that sends and receives the diagnostic packet when the parallel computer system is started up, and a mechanism which sends and receives the diagnostic packet during system operation when the network is not used and periodically and the connected to one another by internal buses 13, 23, and 33, data transfer signals 10, 20, and 30, a service processor(SVP) 5 which is used for the operation of the whole system, and a processor control signal 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network diagnosing method for a parallel computer which transfers data between processors by a network connecting a plurality of processors.

[0002]

2. Description of the Related Art In a conventional system in which a plurality of computers are connected by a computer network such as a LAN, a conventional technique for testing whether or not there is a network failure when connected by Ethernet, for example, W. Richard. UN in P527-550 of "UNIX Network Programming" (published by Toppan) by Steguns
A ping routine in the IX system is described.

[0003]

UNI, which is the prior art
The ping command in the X system is not considered for a parallel computer that connects a plurality of processors via a network and transfers data between the processors. Also, p
The ing command is enabled by the user manually issuing a command, and while the system is operating,
If the data signal line between the processors is inadvertently cut, or if any processor or the hardware configuring the network fails due to some disturbance, it is difficult to find the failed part. If the number of processors is small, it is possible to manually point out the faulty part by using the conventional method or the service processor, but if the number of processors becomes large like a massively parallel computer, it will take considerable time and man-hours to find the faulty part. It will cost you.

Many parallel computers are likely to connect a plurality of processors with a large amount of cables, and the cables also increase in proportion to the increase in the number of processors, so that the parallel computers have a higher processing capacity than the conventional computers. However, if the failure handling is not strengthened, the system operation rate may decrease.

[0005]

In order to solve the above problems, in a parallel computer which transfers data between processors by a network in which a plurality of processors are connected, each processor automatically executes conventional network diagnostic test means for itself. It has a control means for self-test.

Further, a processor dedicated to diagnosis is provided on the network in addition to a processor for performing normal calculation, and the processor dedicated to diagnosis has a control means for automatically performing the conventional network diagnostic test means.

Further, the conventional network diagnostic test means has a control means that is automatically executed by each processor when the system is started up.

Further, it has a control means for automatically performing the conventional network diagnostic test means when the network is not in use while the system is in operation or periodically.

[0009]

In the parallel computer according to the present invention, a diagnostic packet for diagnosing a network failure and reporting to the OS and the user is used between the interprocessor network and a plurality of processors connected to the network. By automatically performing a diagnostic test and performing a self-test on itself, it becomes possible for the processor to be aware of whether it can normally perform data transmission / reception processing to the network.

Further, a processor dedicated to diagnosis is provided on the network in addition to the processor for performing normal calculation, and only this processor is automatically diagnosed, so that the calculation processing of other calculation processors is not hindered. Diagnosis can be performed, and it is possible to prevent deterioration of the processing capacity of the entire system due to the diagnostic test.

Further, since each processor automatically carries out a diagnostic test when the system is started up, it is possible that the system may start operating while any of the processors or the hardware constituting the network is out of order and malfunction. It is possible to prevent it.

Further, since each processor automatically performs a diagnostic test when the network is not used or periodically while the system is in operation, the network can be diagnosed without the user issuing a command while the system is in operation. Even if any processor or hardware constituting the network fails due to a disturbance, it is reported early, so that it is possible to continue operating the system with the failure and prevent malfunction.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

First, the configuration of the parallel computer according to the present invention will be described.

FIG. 1 shows a parallel computer according to the present invention.
To detect whether or not the hardware on the network, which is different from the inter-processor data communication used for actual calculation, is connected by connecting n arithmetic processors to the network and performing the inter-processor data transfer. 1 shows the configuration of a parallel computer that also performs dedicated communication for network diagnosis. In FIG. 1, reference numerals 1 and 2 denote processors (PU (1), ..., P
U (n)) is shown. Each processor 1, 2 is a CPU 11,
21 and memories 12, 22 and network interface circuits 14, 24, which are connected via processor internal buses 13, 23, respectively. Each processor is
The data transfer signals 10 and 20 are connected to the network 4 for interprocessor coupling. A service processor (SVP) 5 is connected to each of the processors 1 and 2 via a processor control signal 6.

FIG. 2 is one of the circuits constituting the processor described in FIG. 1, and is a network interface circuit 14 which is an interface for transferring data between the processors 1 and 2 and the interprocessor coupling network 4. The internal structure of is shown. In FIG. 2, a network interface circuit 14 has a function of reading data from a transmission packet area of a memory in a processor, transmitting the data to the network, and automatically generating a diagnostic packet. When receiving data from, writing data to the receive packet area of the memory in the processor or receiving a diagnostic packet,
A receiving circuit 102 having a function of transferring a diagnostic packet to the diagnostic circuit, a network control register (NCR) 104 for holding a control command for controlling the network interface circuit, and a network status indicating a state inside the network interface circuit. When a diagnostic packet is received from the register (NSR) 103, the received diagnostic packet, the network diagnostic circuit 106 that diagnoses the network, and another processor, the packet header is rewritten and sent back to the original processor via the network. A packet header rewriting circuit 107 and a timer monitoring circuit 105 for monitoring time are provided.

The transmission circuit 101 uses the bus data input signal 1
When a packet is received from the packet transmission area on the processor internal memory via 10, the packet transmission signal 111
Send to the network at. Also, when a diagnostic packet created by the OS or the like is input from the internal bus 13 via the bus data input signal 110 or a diagnostic packet is generated inside the transmission circuit, a transmission diagnostic packet output signal 112
When the transmission diagnostic packet is output to the diagnostic circuit 106 via the transmission diagnostic packet input signal of the packet header conversion circuits 107 to 113, the return packet in which the packet header is unconditionally rewritten is transmitted as a packet. It has a function of outputting to the network via the signal 111. Furthermore, when the diagnosis is set to be periodically performed, the timer monitoring circuit 105 also has a function of transmitting a diagnostic packet at regular time intervals by a timer signal. In addition, the next diagnostic packet is output until the diagnostic process is completed, such as receiving the diagnostic packet received by the value of the network status register (NSR) after sending the diagnostic packet once, or disappearing the diagnostic packet and timing out. do not do.

Upon receiving a packet from the network via the packet reception signal 121, the reception circuit 102 outputs the packet to the packet reception area on the memory via the bus data output signal 120 via the processor internal bus. In addition, a diagnostic packet from another processor or the transmission circuit 10 of the own processor is transmitted via the packet reception signal 121.
When the diagnostic packet transmitted by the processor 1 is a diagnostic packet from another processor, the diagnostic packet is output to the packet header conversion circuit 107 via the return packet output signal 123, and the diagnostic packet transmitted by the transmission circuit 101 inside the processor itself. In the case of, it has a function of outputting a packet to the diagnostic circuit 106 via the received diagnostic packet output signal 122.

Network status register (NS
R) 103 aggregates data of the transmission circuit status signal 141 from the transmission circuit 101, the reception circuit status signal 142 from the reception circuit 102, and the diagnostic circuit status signal 143 from the diagnostic circuit 106, and the processor internal bus 13 and the transmission circuit. Network status signal 1 to 101
40 is output.

Network control register (NC
The R) 104 receives a network control command from the processor internal bus 13 via the network control signal 130, and outputs a transmission circuit control signal 131 to the transmission circuit 101.

The diagnostic circuit 106 compares the transmission diagnostic packet from the transmission circuit 101 and the reception diagnostic packet from the reception circuit 102, makes a determination, and reports the result to the network status register (NSR) 103. At this time, using the timer signal 150 from the timer monitoring circuit 105, if the reception diagnostic packet is not input within a fixed period after the transmission diagnostic packet is input, it is regarded as a timeout error and the network status register (NSR) 10
Report the results to 3. The contents to be reported are the address of the diagnosed processor and the diagnosis result, which indicates a normal end, a packet compare error, or a timeout error.

The timer monitoring circuit 105 includes a circuit inside the processor, a transmission circuit 101, and a diagnostic circuit 10 at regular intervals.
6 outputs the timer signal 150. Functions as a timer interrupt generation circuit.

When the diagnostic packet is input from the receiving circuit 102 via the return packet output signal 123, the packet header rewriting circuit 107 converts the type of packet from the transmitting diagnostic packet to the receiving diagnostic packet, and at the same time, the source processor address and It has a function of swapping destination processor addresses and outputting a diagnostic packet after packet header rewriting to the transmission circuit 101 via the return packet input signal 113.

FIG. 3 shows the internal structure of the transmission circuit 101 which is one of the circuits constituting the network interface circuit 14 described with reference to FIG. In FIG. 3, the transmission circuit 10
1 is a transmission circuit control signal 131, a network status signal 140, and a transmission circuit control circuit 1101 that controls the inside of the transmission circuit 101 by a timer signal, a transmission buffer 1102 that outputs a packet to the network, and a diagnostic packet inside the transmission circuit 101 automatically. The diagnostic packet creation circuit 1103 created in 1) and the packet code analysis circuit 1104 for reading the flag in the packet on the memory created by the OS or the like and determining whether the packet is a normal packet or a diagnostic packet.

In addition to these large-scale circuits, a normal / diagnostic switch 1111 for switching the transmission path depending on whether the packet from the processor internal bus 13 is a normal packet or a diagnostic packet, and a diagnostic packet for switching the diagnostic packet creation method. Creation means switching selector 111
2, a normal / diagnostic packet selector 1113 that switches between outputting a normal packet and a diagnostic packet, and a loopback packet selector 1114 that switches between outputting a loopback packet and a normal / diagnostic packet.

The transmission circuit control circuit 1101 has a transmission circuit control signal 131 from the network control register (NCR) 104 and a network status signal 1 from the network status register (NSR) 103.
40 and timer signal 15 from the timer monitoring circuit 105
0 is input and the content is analyzed, and the automatic diagnostic packet creation signal 1161 is sent to the automatic diagnostic packet creation circuit 1104, the diagnostic packet creation means switching signal 1162 is sent to the diagnostic packet creation means switching selector 1112, and the normal / diagnostic packet transmission switching signal 1163 is sent. The normal / diagnosis packet selector 1113 outputs the return packet transmission switching signal 1164 to the return packet selector 1151 to control the packet transmission path in the transmission circuit.

The transmission buffer 1102 receives the OS from the processor internal bus 13 via the bus data input signal 110.
Is a buffer for receiving the packet created in the packet transmission area on the memory 12. At the same time, it is determined whether or not this buffer is in use via the transmission circuit status signal 141 via the network status register (NSR) 10
Report to 3.

The diagnostic packet creation circuit 1103 receives the diagnostic packet creation signal 1161 from the transmission circuit control circuit 1101.
When a diagnostic packet creation command is received via, a diagnostic packet is automatically created and the packet is output to the packet transmission path.

The packet code analysis circuit 1104 reads only the packet code of the packet input from the bus data input signal 110 and determines whether the type of the packet input from the internal bus 13 is a normal packet or a diagnostic packet. The transmission packet code analysis report signal 1171 is output to the / diagnosis switch 1111 to switch the packet transmission path.

Similar to FIG. 3, FIG. 4 shows the internal structure of the receiving circuit 102, which is one of the circuits constituting the network interface circuit 14 described in FIG. In FIG. 4, the receiving circuit 102 reads a packet from the network 4 for receiving a packet from the network 4 and a packet code input to the receiving buffer 1201 to determine whether the packet type is a normal packet, a diagnostic packet, or a return diagnostic packet. The results of the receiving circuit status reporting circuit 1203 and the packet code analyzing circuit 1202 that collect the statuses of the circuits forming the receiving circuit such as the analyzing circuit 1202, the receiving buffer 1201 and the packet code analyzing circuit 1202 and report them to the network status register (NSR) 103. Return packet switching switch 1211 for switching the reception path by
The diagnostic packet changeover switch 1212 and the like are provided.

The reception buffer 1201 fetches a packet from the network 4 via the packet reception signal 121,
The packet is output to the reception packet path (1) 1221, and at the same time, a report of the packet reception status in the reception buffer 1201 is output to the reception circuit status reporting circuit 1203 via the reception buffer status reporting signal 1230.

The packet code analysis circuit 1202 reads only the packet code of the received packet input from the network 4 via the packet reception signal 121,
Based on the value, it is determined whether the received packet is a normal packet, a reception diagnostic packet or a transmission diagnostic packet, and the result is sent to the reception circuit status reporting circuit 1203 via the normal / diagnosis packet reception report signal 1240 and the return packet reception report signal 1250. Output to. At the same time, the return packet switching switch 1211 and the normal / diagnostic packet switching switch 1212 are controlled to switch the packet receiving path inside the receiving circuit.

The receiving circuit status reporting circuit 1203 receives the receiving buffer status reporting signal 1 from the receiving buffer 1201.
230 from the packet code analysis circuit 1202
The diagnostic packet reception report signal 1240 and the return packet reception report signal 1250 are received, and the contents are output to the network status register (NSR) 103 via the reception circuit status signal 142.

FIG. 5 shows a packet format used for data transfer between processors of the parallel computer according to the present invention. In FIG. 5, the packet includes a packet header indicating the beginning of the packet and packet data indicating the contents. The packet header is composed of a packet code indicating the type of packet, a packet length indicating the size of the packet, a source processor address indicating the source and a destination processor address indicating the destination.

The packet code indicates the type of packet as described above. Specifically, it is a normal packet used during normal operation and a transmission diagnostic packet for the other processor to diagnose other processors. The value is changed by the received diagnostic packet, which is a reply of the diagnostic packet from the processor, and the normal communication packet is "0" in this embodiment.
0 ", the transmission diagnostic packet is" 01 ", and the reception diagnostic packet is" 10 ".

The packet length indicates the number of packet data included in the packet, and in the case of a diagnostic packet, the packet data is set to 2 in order to facilitate the analysis.

Since a value different for each processor is assigned by the service processor SVP when the parallel computer is started up, the address of the transmission / reception processor is set by referring to that value.

In the case of a diagnostic packet, the packet data is dummy data. To facilitate analysis, the first packet data is set to all "0" and the second packet data is set to all "F".

FIG. 6 shows a parallel computer according to the present invention, n
1 shows a configuration of a parallel computer that connects each arithmetic processor and a processor dedicated to diagnosis to a network and performs data transfer between processors and transmission / reception of a diagnostic packet for diagnosing the network. In FIG. 6, reference numerals 1 and 2 denote arithmetic processors (P
U (1), ..., PU (n)) are shown, and 3 is a diagnosis dedicated processor (PU (n + 1)). Each processor 1, 2,
3 is CPUs 11, 21, 31 and memories 12, 22, 32
And network interface circuits 14, 24, 3
4, each of which has a processor internal bus 13, 23,
It is connected via 33. Each processor 1, 2, 3
The data transfer signals 10, 20, 30 are connected to the network 4 for interprocessor coupling. A service processor (SVP) 5 is connected to each of the processors 1, 2, and 3 via a processor control signal 6.

Next, the operation of the parallel computer according to this embodiment will be described.

When the system is started up, the service processor (SVP) 5 uses the configuration information of this parallel computer to send the addresses and the addresses on the network 4 that configure the parallel computers to the processors 1 and 2 via the processor control signal 6. After the network configuration information is distributed and the distribution is completed, the inside of each processor starts the startup processing. Each of the processors 1 and 2 issues a self-test request to the network interface circuit 14 upon starting the apparatus start-up process. Therefore, the network control register (NCR) in the network interface circuit 14 issues an instruction to transmit a transmission diagnostic packet to its own processor. Upon receiving the command, the transmission circuit 101 in the network interface circuit 14 causes the transmission diagnostic packet addressed to the own processor 1 to automatically generate the diagnostic packet 1104.
And the transmission diagnostic packet is stored in the diagnostic circuit 106 at the same time. After transmission to the network 4, the destination processor address of the transmission diagnostic packet is addressed to the own processor 1, so the transmission diagnostic packet is received as it is from the network 4 in the network interface circuit 14. Receiving circuit 1 in network interface circuit 14 for receiving packets
When the packet 02 is received, the packet is a transmission diagnostic packet, and therefore the packet is sent back to the address of the processor that has transmitted it. When the packet code analysis circuit 1202 in the reception circuit 102 analyzes the transmission diagnostic packet, the loopback packet changeover switch 1211 is switched to the loopback packet processing side, and the packet header rewriting circuit 107 rewrites the packet code to the code “10” of the reception diagnostic packet. After that, the packet is transferred to the transmission circuit 101, and the reception diagnostic packet is transmitted from the transmission circuit 101 to the network 4 again. When network 2 receives this packet,
Since the destination processor address is the same, this packet is sent back to the own processor 1 again. Own processor 1
However, when the reception diagnostic packet is received by the reception circuit 102 inside the network interface circuit 14, the packet code analysis circuit 1202 analyzes the packet code and determines that it is a reception diagnostic packet. Then, the return packet changeover switch 1211 and the normal / diagnosis packet changeover switch 1212 are controlled to transfer the received packet to the network diagnosis circuit 106. When the network diagnostic circuit 106 receives the received diagnostic packet, it compares the received diagnostic packet with the previously stored transmitted diagnostic packet, and if the packet is correct, the network status circuit (NSR) indicates that the network and the network interface circuit 14 of its own processor 1 are normal. ) 103. When these operations are completed, the CPU 11 refers to the network status register (NSR), and if there is no problem, the self-test ends normally, but if a transmission / reception diagnostic packet is not received, a timeout is returned and even if it is received successfully. If the diagnostic result is bad, a diagnostic packet compare error is returned. When these defects occur in the self-test, it reports to the service processor (SVP) 5 that its own processor 1 is defective.

When the self test ends normally, the self processor 1 diagnoses the other processors 2. This is because the packet is created by the diagnostic packet creation circuit 1104 in the same manner as the self-packet,
This time, like the self-packet, the destination address is set not to the own processor 1 but to the other processor 2, and the transmission circuit 101 inside the network interface circuit 14 transmits to the other processor 2 via the network 4. To do. Other processor 2 is its own processor 1
When the transmission diagnostic packet from the network interface circuit 24 is received by the network interface circuit 24, the packet code is converted into the reception diagnostic packet in the same manner as the self-test, and the source address and the destination address are swapped, and the self-processor 1 is transmitted via the network 4. Send it back to. When the processor 1 receives the reception diagnostic packet, the reception circuit 102 inside the network interface circuit 14 transmits the reception diagnostic packet to the network interface circuit 14
The packet is transferred to the internal network diagnostic circuit 106, compared with the transmission diagnostic packet transmitted previously, and the comparison result is reported to the network status register (NSR) 103.
After that, the CPU 11 reads the value of the network status register (NSR) 103 and determines whether the processor 2 diagnosed this time is normal or abnormal. When the diagnosis is completed for the other processors 2, the diagnostic packet is transmitted to the next processor, and this is repeated for all the processors in order.

When each of the processors 1 and 2 completes the diagnosis of all the processors, the system starts to operate,
Booting of OS etc. is started.

Diagnosis during system operation is performed by transmitting / receiving a diagnostic packet by a software routine from a user command or OS, which is a conventional technique, and by the network interface circuit 14 automatically creating a diagnostic packet and transmitting / receiving it to the network. There are two types. In transmitting and receiving a diagnostic packet by a software routine from a user command, which is a conventional technique, first, a dummy packet is created in the transmission packet area on the memory 12, and is transmitted and received as a normal packet to a processor to be diagnosed and transmitted. A method in which the OS analyzes / determines the packet and the received packet by software, and a packet is created in the memory as a transmission diagnostic packet and transmitted to another processor 2, which converts it into a reception diagnostic packet. There is a method in which the self-processor 1 receives a packet that has been transmitted as a return packet, the network interface circuit 14 analyzes it in terms of hardware, and the OS refers to the result to determine.

In order to automatically generate a diagnostic packet by the network interface circuit 14 and send / receive it to / from the network, the OS issues a command to the network interface circuit 14 to automatically generate a diagnostic packet for diagnosis, The diagnostic packet creation circuit 1103 inside the circuit 14 automatically generates a diagnostic packet, transmits / receives the diagnostic packet to / from another processor 2, analyzes it by hardware in the network diagnostic circuit 106, and the result is displayed by the OS. The method of referring to and making a decision, and the OS sets the network interface circuit 14 in advance to a mode in which a diagnostic packet is automatically generated and a diagnosis is performed if the network is unused, and the CPU 11 Is If not, the diagnostic packet is automatically generated inside the network interface circuit 14, the diagnostic packet is transmitted / received to / from another processor 2, and the network diagnostic circuit 106 analyzes it by hardware. Is reported to the OS, and the OS sets the network interface circuit 14 to a mode in which it issues a diagnostic packet at regular intervals.
4 Inside the timer monitoring circuit 105 timer signal 150
, A diagnostic packet is automatically generated at regular intervals, the diagnostic packet is transmitted / received to / from another processor 2, and the network diagnostic circuit 106 analyzes it in terms of hardware.
If the result is abnormal, there is a method of reporting to the OS.

Next, the operation in the case of connecting to the network 4 the diagnosis-dedicated processor 3 in addition to the plurality of processors 1 and 2 for performing the normal operation in addition to the parallel computer system described above will be described below. . When the system is started up, the service processor (SVP) 5 is based on the configuration information of the parallel computer, and via the processor control signal 6, the arithmetic processors 1 and 2 and the dedicated diagnostic processor 3 on the network 4 that constitutes the parallel computer. Addresses and network configuration information are distributed, and after the distribution is completed, the processing inside each processor is started. When each of the arithmetic processors 1 and 2 and the diagnostic processor 3 enters the device start-up processing, it issues a self-test request to the network interface circuit inside each processor and executes the self-test processing as described above. To do. When the self-test process is completed, the arithmetic processors 1 and 2 are service processors (S
The system waits for a while until the VP) 5 reports the end of the system startup processing. Here, only the diagnosis-dedicated processor 3 operates to perform a diagnosis process on each of the arithmetic processors 1 and 2. When the diagnosis-dedicated processor 3 finishes the diagnosis processing for all the processors, the diagnosis-dedicated processor 3 reports the completion of the diagnosis processing for all the processors to the service processor (SVP) 5, and the service processor (SVP)
When the VP 5 receives it, the service processor (SV
P) 5 reports the completion of the system startup processing to all the processors. When all the processors receive a report from the service processor (SVP) 5 that the system startup processing has been completed, all the processors enter the boot processing of the OS or the like and the system operation starts. With this configuration, in the network diagnostic test during system operation, the diagnostic packet is not transmitted / received from the arithmetic processors 1 and 2, but the network diagnostic dedicated processor 3
Only the transmission and reception of the diagnostic packet and the self-test with respect to the arithmetic processors 1 and 2 are performed. When a failure or the like of another processor is found in the network diagnosis processing by the network diagnosis dedicated processor 3, the arithmetic processors 1 and 2 do not perform the diagnosis processing, and therefore it is possible to grasp the existence of the failure processor from oneself. Although not possible, the diagnosis-dedicated processor 3 can find a faulty processor by the diagnosis-dedicated processor 3 performing a network diagnosis process. When the diagnostic-dedicated processor 3 finds a failure in the arithmetic processor, it broadcasts to all the arithmetic processors 1 and 2 via the network 4 using a normal packet and reports the result. This diagnostic-dedicated processor constantly sends and receives diagnostic packets to and from its own processors 1, 2 and 3, and normal packets are broadcast reports to the arithmetic processors 1 and 2 when a failed processor is found in the diagnostic packet analysis result. Only when

[0047]

As described above, according to the present invention,
A dedicated packet for diagnosis that diagnoses the failure of the hardware configuring the network or other processors for the network or other processors at the time of system startup or system operation in a parallel computer that transfers data between processors by a network connecting multiple processors Since it becomes possible to detect a failure early by transmitting and receiving, the operating rate of the computer system is increased. Also, while the system is in operation, it switches to a normal data transfer path to send and receive diagnostic packets, so it is safe without collision with normal data communication,
Further, since the diagnostic packet is transmitted / received when the network is not used or at regular intervals, the use efficiency of the network is improved.

Further, by providing a processor dedicated to diagnosis in addition to the arithmetic processor, it is possible to prevent a decrease in the processing capacity of the CPU and the entire system due to frequent transmission and reception of diagnostic packets.

[Brief description of drawings]

FIG. 1 shows an outline of a configuration of a parallel computer according to an embodiment of the present invention.

FIG. 2 shows a configuration of a network interface circuit of a parallel computer according to an embodiment of the present invention.

FIG. 3 shows a configuration of a transmission circuit inside a network interface circuit according to an embodiment of the present invention.

FIG. 4 shows a configuration of a receiving circuit inside a network interface circuit according to an embodiment of the present invention.

FIG. 5 shows a packet format used for data transfer between processors of a parallel computer according to an embodiment of the present invention.

FIG. 6 shows an outline of a configuration of a parallel computer according to an embodiment of the present invention.

[Explanation of symbols]

1 ... Processor (PU (1)), 2 ... Processor (PU (n)), 3 ... Processor (PU (n + 1)), 4
... network, 5 ... service processor (SVP),
6 ... Processor control signal, 7 ... Network control signal,
10 ... Data transfer signal (PU (1)), 11 ... CPU
(PU (1)), 12 ... Memory (PU (1)),
13 ... Processor internal bus (PU (1)), 14 ... Network interface circuit (PU (1)), 20 ... Data transfer signal (PU (n)), 21 ... CPU (PU (n)), 22
... memory (PU (n)), 23 ... processor internal bus (PU (n)), 24 ... network interface circuit (PU (n)), 30 ... data transfer signal (PU (n + 1)),
31 ... CPU (PU (n + 1)), 32 ... Memory (PU
(N + 1)), 33 ... Processor internal bus (PU (n +
1)), 34 ... Network interface circuit (PU)
(N + 1)), 40 ... Network circuit failure report latch,
101 ... Transmission circuit (PU (1)), 102 ... Reception circuit (PU)
(1)), 201 ... Transmitting circuit (PU (n)), 20
2 ... Receiving circuit (PU (n)), 301 ... Transmitting circuit
(PU (n + 1)), 302 ... Receiving circuit (PU (n + 1)), 1
03 ... Network Status Register (NSR), 10
4 ... Network control register (NCR), 105
… Timer monitoring circuit, 106… Packet diagnostic circuit, 107… Header rewriting circuit, 110… Bus data input signal, 111… Packet transmission signal, 112…
Transmission diagnostic packet output signal, 113 ... Return packet input signal, 120 ... Bus data output signal, 121 ... Packet reception signal, 122 ... Reception diagnostic packet output signal, 12
3 ... Return packet output signal, 130 ... Network control signal, 131 ... Transmission circuit control signal, 14
0 ... Network status signal, 141 ... Transmission circuit status signal, 142 ... Reception circuit status signal, 143 ... Diagnostic circuit status signal, 150 ... Timer signal, 1101 ...
Transmission circuit control circuit, 1102 ... Transmission buffer, 1103
... packet code analysis circuit, 1104 ... diagnostic packet creation circuit, 1111 ... normal / diagnosis changeover switch, 1112 ... diagnostic packet creation means changeover selector, 1113 ... normal / diagnosis packet selector, 1114 ... normal / turnback packet selector, 1121 ... transmission packet Transfer path (1), 1131 ... normal packet transfer path, 1132 ... diagnostic packet transfer path,
1133 ... Automatically created diagnostic packet transfer path, 1141 ... Transmission packet transfer path (2), 1151 ... Diagnostic packet creation signal, 1152
... diagnostic packet creating means switching signal, 1153 ... normal / diagnostic packet transmission switching signal, 1154 ... return packet switching signal, 1161 ... normal / diagnostic packet input switching signal, 1201 ... receiving buffer, 1202 ...
Packet code analysis circuit, 1203 ... Reception circuit status reporting circuit, 1211 ... Return packet changeover switch, 12
12 ... Normal / diagnosis packet changeover switch, 1221 ... Reception packet path (1), 1222 ... Reception packet path (2), 1230 ... Reception buffer status report signal, 1240 ... Normal / diagnosis packet reception report signal, 1250 ... Return packet reception Report signal.

Claims (5)

[Claims] 1. A parallel computer which transfers data between processors by a network connecting a plurality of processors, detects whether or not hardware on the network, which is different from data communication between processors used for actual calculation, has failed. A parallel computer that transfers diagnostic packets to the network and diagnoses between each processor and the network to identify the faulty part and report to the OS and users. 2. The parallel computer according to claim 1, wherein each processor transfers a diagnostic packet to itself and performs a self-test in a parallel computer which transfers data between processors by a network connecting a plurality of processors. calculator. 3. In a parallel computer for transferring data between processors by a network connecting a plurality of processors, a processor dedicated to diagnosis is separately connected on the network in addition to a processor for calculation used for actual calculation, and this processor is connected to the network or The parallel computer according to claim 1, wherein a diagnostic packet is transmitted to and received from another processor to diagnose the hardware constituting the network and the other processor. 4. In a parallel computer for transferring data between processors by a network connecting a plurality of processors, the processor transfers a diagnostic packet to the network at the time of system startup to diagnose hardware constituting the network and other processors. The parallel computer according to claim 1. 5. In a parallel computer for transferring data between processors by a network connecting a plurality of processors, diagnostic packets are periodically transferred onto the network when the network is not in use during system operation or when a timer or the like is used. The parallel computer according to claim 1, which diagnoses hardware and other processors constituting the computer.