JPS63293949A - Forming method for multilayer interconnection - Google Patents

Abstract

PURPOSE:To avoid the possibility of step coverage, and maintain the flatness of a surface, by forming an interlayer insulating film by burying a first wiring layer, etching back this film, exposing a protruding part of the first wiring layer, and then forming a second wiring layer thereon, which is connected with the wiring of the first layer, via the above protruding part. CONSTITUTION:On a base insulating film 2 of SiO2 or the like, an Al film 3 of about 2.0 mum thick is formed by sputtering Al. A second photoresist mask 6 is formed on a part of the Al layer 3, and Al etching is performed. The Al film 3 is left as an Al wiring pattern 7 of 1mum thick, and a part covered by the second photoresist mask protrudes as a part 8 to connect upper and lower wirings. An interlayer insulating material 9 is thickly deposited so as to bury the whole Al film. The surface of the interlayer insulating film is subjected to etch back by sputter-etching and the like, and etching is performed to a depth wherein the upper part of the protruding part 8 is exposed. On the whole surface, Al is sputtered, and patterning is performed by photo etching to form a pattern of a second Al wiring 10 connected with the first layer wiring at the protruding part 8. Thereby, a multilayer interconnection is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a doll (aluminum) fat distribution technology, and particularly to a technology for forming fine multilayer wiring.

[Prior art]

Regarding A1 multilayer wiring, please refer to the September 1985 issue of NIKKEI MICRODEVI published by Japan-Germany McGraw-Hill.
It is described in CES pages 71 to 86, and the outline is as follows: (1) As shown in Figure 10, the wiring (
When making contact between A4) and the substrate (Si),
A contact hole is formed in the surface insulating film such as by sputtering or etching, and AA is sputtered thereon. Alternatively, (21 When connecting the upper and lower two layers of A! wiring 5.16 formed via an interlayer insulating film as shown in FIGS. 11 and 12, an insulating film such as CV D = S io* A technique is known in which a through hole 14 is formed in 9 or the like and 81 is sputtered from above to form the upper layer AA wiring 16.

[Problem that the invention seeks to solve]

When the diameter of the contact hole in memory LSI etc. is reduced to 1 μm or less, the aspect ratio of the fine hole (b/a ”
) becomes larger, the formation of the hole itself and the step coverage of the upper layer A1 film that makes contact through the hole deteriorate, and the contact resistance due to the contact force increases.
In addition, many problems were unavoidable, such as the flattening of the surface, which combined with the miniaturization of the wiring, increased the current density, causing breakage of the upper wiring.

The present invention has been made to overcome the above-mentioned problems, and its purpose is to completely eliminate the risk of step coverage of the upper layers A and 6 in the contact area, and to improve conductivity between wirings. An object of the present invention is to provide a method for forming multilayer wiring that can ensure surface flattening.

[Means for Solving the Problems] A brief summary of typical inventions disclosed in this application is as follows.

That is, by forming a first layer wiring that partially protrudes thickly on the substrate, burying this first layer wiring to form an insulating film between the eyebrows, and etching back this interlayer insulating film, the protrusion of the first layer wiring is reduced. After exposing the surface of the exposed portion, a second layer wiring is formed thereon and connected to the first layer wiring through the protrusion.

[For production]

According to the above-mentioned means, there are no through holes for connecting the upper and lower wires from the beginning, so step coverage defects due to A and 6 sputters to the through holes do not occur, and the surface of the upper wire is flattened. Therefore, the above objective can be achieved.

〔Example〕

FIGS. 1 to 6 show an embodiment of the present invention, and are process sectional views of a process for forming multilayer wiring in an IC.

Each step will be explained in detail below.

[11 A semiconductor substrate 1 such as Si is prepared with a semiconductor element region (not shown) formed on the surface thereof by means such as selective impurity diffusion, and as shown in FIG. AA is sputtered to produce AAAs2 with a thickness of about 2.0 μm.

A first photoresist mask 4 for forming a first layer wiring pattern is formed thereon.

(2) By etching A4 to a depth of about 1 μm through the first photoresist mask 4, a thickness of about 1 μm is formed in the areas not covered by the mask, as shown in FIG.
The A2 film portion 3 covered with the mask has a thickness of 2 μm.
Maintains the thickness of After this, A4 with a thickness of 2 μm
A second photoresist mask 6 is formed over a portion of layer 3.

(3) In this state! As shown in FIG. 3, the An film (5) with a thickness of 1 μm is etched away, while the film 2 with a thickness of 2 μm (31 is a film with a thickness of 1 μm).
The part that remains as the An wiring pattern 7 and is covered with the second photoresist mask is the part 8 that connects the upper and lower wires.
stands out as

+41 Add interlayer insulation material 9 to embed the AA film on the entire surface.
deposits thickly. As shown in FIG. 4, this glabellar insulating material 9 is formed by spin-coating an inorganic glass such as 5OG (spin-on glass) or an organic glass such as polyimide resin to a thickness exceeding 2 μm. .

(5) Etch back the surface of the interlayer insulating film by sputter etching or the like to a depth that exposes the upper surface of the protrusion 8 of the first layer gate, as shown in FIG.

(A stone is sputtered on the entire surface of the 61, and then buttering is performed by photoetching to form a pattern of the second layer A1 wiring 10 connected to the first layer wiring at the protrusion 8 as shown in FIG. Wiring formation is completed.

According to the above means, the effect can be obtained for the following reasons.

(1) Since the portion for connecting the upper and lower wirings is formed as a protrusion of the lower layer wiring and is buried with an interlayer insulating film, there are no through holes from the beginning.

(21 Since there are no through holes, there is no longer any difficulty in microfabrication of through holes.

(Step coverage defects do not occur when connecting the second layer wiring to the first layer wiring through the 31 through holes.

(Since there is no risk of 41-step coverage failure, there will be no conduction failure between wirings.

(51) Since no through holes are formed in the interlayer film, flattening of the surface of the insulating film can be ensured.

(6) Since there are no through holes and it can be flattened, the upper layer (second layer) wiring can be miniaturized and its reliability can be improved.

(7) Formation of the protrusion of the lower wiring, embedding with an insulating film, and etching back can be performed by applying existing techniques as they are.

(8) With the above (2) and (61), microfabrication of multilayer wiring has become very practical.

Although the invention made by the present inventor has been specifically explained based on the examples, the present invention is not limited to the above-mentioned examples, and can be modified at will without departing from the gist thereof.

For example, when providing a protrusion on the first layer wiring, the following steps can be performed.

As shown in Figure 7, there is a layer of K1 μm thick on the underlying insulating film! A film is formed and patterned to form a pattern for the first layer A1 wiring.

As shown in Figure 8, after coating the entire surface with photoresist, the portions corresponding to the through holes (protruding portions) are removed by photoetching, and AA is sputtered (or evaporated) over the entire surface.
Next, an M film 13 is formed on the portion of the first layer A1 wiring where there is no photoresist and on the photoresist.

By dissolving and removing the photoresist with a solvent, the A1 film on the photoresist is "lifted off" and the person on the first layer A2 wiring is removed! Only the protrusion 13 is left as the protrusion 13. Thereafter, multilayer wiring can be formed by moving to the steps shown in FIGS. 4 to 6 above.

According to the above method, even if step coverage failure occurs in the through-hole corresponding portion after AA sputtering, this is rather a portion separated by lift-off, and does not cause a break in the second layer A1 wiring.

The present invention can be applied to all multilayer wiring structures that require microfabrication.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, there are no defects in the fine wiring structure, and the reliability of the product can be improved.

[Brief explanation of the drawing]

FIGS. 1 to 6 are process cross-sectional views of a two-layer wiring process showing an embodiment of the present invention. FIGS. 7 to 9 are cross-sectional views of a part of a two-layer wiring process showing another embodiment of the present invention. FIG. 10 is a sectional view showing an example of a conventional wiring structure. FIGS. 11 and 12 are partial step sectional views of a conventional two-layer wiring process. 1... Semiconductor substrate (Si), 2... Base insulating film (S
i02), 3... A1 organ, 4... Photoresist mask, 5... People who have become thinner! Wiring, 6... Photoresist mask, 7... First layer A1 wiring, 8... A1
Wiring protrusion, 9... interlayer insulating film, 10... second layer A
1 wiring, 14...through hole.
2-Agent Patent Attorney Katsuo Ogawa Figure 4 Figure 6 Figure 7 Figure r Figure 8 Figure 7, J'-AI Figure 11 Figure 12 Figure 7゜

Claims (1)

[Claims] 1. A step of forming a first layer wiring with a portion thickly protruding on the substrate, a step of burying the first layer wiring to form an interlayer insulating film, and etching back the interlayer insulating film. and above 1st
A multilayer wiring comprising the steps of: exposing the upper surface of a protrusion of a layer wiring; and forming a second layer wiring on the interlayer insulating film and connecting it to the first layer wiring via the projection. Formation method. 2. The multilayer wiring according to claim 1, wherein the first layer wiring is made thinner by applying a corrosion-resistant mask to a part of the wiring which has been formed thick in advance and etching the other part. How to form wiring.