JPS63293879A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the base resistance as well as to improve the frequency characteristics by forming a base and emitter in self alignment, and using as the base extraction electrode a metal silicide layer into which a P-type impurity was doped. CONSTITUTION:After forming on an N-type semiconductor substrate 1 a region isolated by an oxide film 2, a metal silicide layer 3 is stacked on the whole substrate 1 surface, and boron is ion-implanted. Then an oxide film 4 is grown on the layer 3, a hole is selectively opened to expose the substrate 1 surface. An impurity is diffused from the layer 3 into the substrate 1 by a heat treatment to form an external base 7. Then, after growing a second insulating film 6 on the layer 3 in which the base 7 was formed, the film 6 is left only on the sidewalls of the opening section. Then, a P region becoming a intrinsic base is formed in the substrate 1 from the opening. Then a polysilicon layer 11 is grown, arsenic is ion-implanted and a heat treatment is performed to form an emitter region 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an ultra-high speed and ultra-high frequency bipolar transistor.

[Conventional technology]

A typical structure of a conventional bipolar transistor is shown in FIG. 3, for example. This transistor includes an oxide film 2 formed on an N-type substrate 1, a P diffusion layer 7 serving as a base region, an N-type region 8t serving as an emitter region, and an emitter electrode 13 . A base electrode 14 is provided, an N+ layer 16 is further formed, and a collector electrode 15 is provided. These emivta electrode portions 13. Base electrode part 14. Bipolar operation is achieved by the collector electrode section 15.

As a typical figure of merit of this bipolar transistor, the gain bandwidth product fT base resistance r bb/,
CfT has a maximum oscillation frequency fmax, etc., and with the recent spread of high frequency applications, CfT has improved its performance.

, faAx improvement (1rbb' reduction) is desired.

[Problem to be solved by the invention J However, in the conventional structure.

There are many restrictions when trying to change the number of fwhx 'bb'.

First, regarding the base resistance rbb', as shown in the multi-emitter structure in Figure 4, the resistance ρ8゜ electrode spacing Sg
It is expressed as follows using the device parameters of SB Sl.

・・・・・・・・・ (1) Here, n is the number of emitters, ρ3. is the P1 resistance in the intrinsic base region, ρS! is an externally based p+4 resistor.

ρ3. P layer resistance directly under the Habase contact” con
represents the contact resistance s 111n emitter (base) stripe length.

According to this formula, is the emitter miniaturized? By proceeding, the first term of equation (1) can be reduced, but
Since the distance of -C%SR is limited by the alignment accuracy of -10,000%PR, it is difficult to reduce the second term in equation (1). Therefore, it is difficult to drastically improve the base resistance rbb'. I can't figure it out.

Further, %fT is expressed by the following formula.

fT=l/(2π(τ80τb1τ, 10τ work months...
...(2) Here, τe is the emitter original heating time, τb
is the base transit time, τX is the collector depletion layer transit time, τ
0 is the collector filling time, and as is clear from FIG. 3, t and τ of the parasitic base other than the intrinsic base necessary for transistor operation. contribution is large, and no improvement in fT can be expected.

Furthermore, fMAX is expressed by the following equation.

fMAxocFi宕7difference (3) As is clear from this equation, it depends on the improvement of s fT 'bb〆, so with the conventional structure, no significant improvement can be expected. do not have.

Object of non-invention, such a problem f:'Is never solved.

Base resistance rbl) #tl! In addition to making it extremely small,
An object of the present invention is to provide a semiconductor device that can improve high frequency characteristics fT fMAX.

[Steps to solve problems]

The method for manufacturing a semiconductor device of the present invention includes a step of selectively forming an element region in a semiconductor substrate of a first conductivity type, and a step of growing a metal silicide layer on the entire surface of the semiconductor substrate and introducing impurities of a second conductivity type. Then, a first insulating film is grown on the crystalcide layer, and selectively opened to cover the semiconductor substrate surface f.
: a step of diffusing impurities from the silicide layer into the semiconductor substrate by exposure and heat treatment, and this impurity diffusion.

After the second insulating film is grown on the Yukitomo silicide layer.

A step of leaving only the second insulating film on the side wall of the opening by anisotropic etching, and etching a second insulating film from the opening to the semiconductor substrate.
After introducing the IL-type impurity, the polycrystalline silicone process involves growing amorphous silicon, introducing the first conductivity-type impurity, and heat-treating it, and adding the polycrystalline silicon to the region above the opening that will become the emitter. Alternatively, the method may include a step of selectively leaving an amorphous silicon layer, and a step of selectively opening the silicide layer to form a base contact, and forming wiring in the emitter and base contact portions. .

[For production]

According to the configuration of the present invention.

[1] Since the base and emitter regions are formed in a self-aligned manner by the metal silicide layer doped with P-type impurities, and this silicide layer can be used as the base extraction electrode, the second term in equation (1) becomes almost zero. can.

2. Also, since the crystalide layer itself has an extremely low resistance, the base resistance rbb'2 as a whole can be significantly reduced.

(3) Furthermore, since the base and emitter are formed in a self-aligned manner, parasitic bases unnecessary for transistor operation can be significantly reduced, and J'T fMhx can be significantly improved.

[Executive child Ali]

Next, the present invention will be explained in detail using the drawings.

FIGS. 1A to 1C are cross-sectional views explaining the entire process order of an embodiment of the present invention. First, an N-type semiconductor substrate 1 is separated by an oxide film 2 and a region is formed (FIG. 1A). )).

Subsequently, a metal/cryside layer 3 is laminated on the substrate 1 to a thickness of 1000 to 2000 Å using, for example, CVD gold.
Perform boron ion implantation. Here, as the metal used for the 7-reicide layer 3, a high melting point metal such as TiW is preferable (FIG. 1(b)).

Next, an oxide film 4t'' is grown on the silicide layer 3, and anisotropic etching is performed using photolithography to etch the surface of the substrate l.
4 (Figure 1 (C)). Furthermore, a second insulating film 6tl-CVD is formed over the entire surface.

Here, the insulation W6 may be of the same type as the first insulating film 4, or may be of a different type. Subsequently, annealing is performed in a nitrogen atmosphere to remove boron in the crystalline layer 3 from the substrate l.
diffused into the external base 7'f.

Form. Note that this process is based on the intrinsic base (8), which will be described later.
) (Fig. 1(d)).

Next, when RIE is performed over the entire surface, only the upper surface of the second insulating film 6 is removed, leaving only the sidewalls of the openings in the crystalline layer 3. If it collapses here, the P region 8, which will become the intrinsic base, is formed by a method such as thermal diffusion or ion implantation (
Figure 1(e)). Next, a polysilicon layer or an amorphous silicon layer 9 is laminated on the entire surface, and arsenic ions are implanted (see Fig. 1). Furthermore, 900-950'
The N+ region emitter region 10 is formed at a temperature of 0 m degrees, and after t, only the polysilicon 11 on the emitter is selectively left by photolithography (FIG. 1-(g)).

Finally, the insulating film 4 on the crystalcide layer 3 is selectively opened to form the entire base-contact 12, and aluminum or Ti-P
, -Au, etc. to form emitter, paste, and collector electrodes 13, 14, and 15, respectively, to form a semiconductor device 1lllltl.
- Completed (Fig. 1 (h)).

FIGS. 2(a) to 2(h) are cross-sectional views explaining the second embodiment of the present invention in order of all steps, and show an example of application to a semiconductor integrated circuit. First, in FIG. 2(a), an N-type buried layer 22 and an N-type epitaxial layer 23 are sequentially formed on a P-type semiconductor substrate 21, and then elements are isolated using an oxide film 2 or the like. Next, a high concentration of N is connected to the collector.
After forming a collector region 24t containing a type impurity (phosphorus), a crystalline layer 3fI:FJ2 is lengthened and boron ions are fully implanted. Figure 2(b)). As a result, the subsequent steps are similar to those of the first embodiment, and finally the semiconductor device shown in FIG. 2 (hl) can be obtained.

〔Effect of the invention〕

As explained above, the present invention has the following effects on improving the characteristics of bipolar transistors.

(1) The base and emitter can be formed in a self-aligned manner.Not only does it eliminate the need for an alignment margin between the base and emitter, but the base resistance 'bb- can be significantly reduced by using 7reside for the extraction electrode. can be reduced to

(2) Since the t1 base and emitter can be formed in a self-aligned manner, the external base, that is, the parasitic base, can be reduced.
fA fMAX will also be significantly improved.

[Brief explanation of drawings]

Figures 1 (a) to (hl) and Figures 2 (al to h) are cross-sectional views explaining the first and second embodiments of the present invention in the order of steps, and Figure 3 is a cross-sectional view of an example of a transistor with a conventional structure. Cross-sectional view, FIG. 4 is a cross-sectional view for explaining the base resistor rbbI in FIG. 3. 1...N-type substrate, 2... Oxide film, 3.
...silicide layer, 4...first insulating film,
5...Resist, 6...Second insulating film,
7...P diffusion layer (emitter region), 8...
... P region (intrinsic base), 9 ... Poly7 lyco/layer, 10 ... N type region (base region), 12
・・・・・・Base contact, 13・Mountain・Emiv 7
1iE electrode, 14...Base electrode, 15...
...Collector electrode, 16...N+ layer, 21...
...P-type semiconductor substrate, 22...Buried layer, 2
3...Epitaxial layer, 24...Collector layer. Agent: Uchihara T/': “Shin and 1”
5)'-4-\ノ

Claims (1)

[Claims] selectively forming an element region on a first conductivity type semiconductor substrate; growing a metal silicide layer over the entire surface of the semiconductor substrate and introducing second conductivity type impurities; and forming a first insulating layer on the silicide layer. A step of growing a film, exposing the surface of the semiconductor substrate by selectively opening it, and diffusing impurities from the silicide layer to the semiconductor substrate by heat treatment, and adding a second layer to the silicide layer after the impurity diffusion. After the insulating film is grown, there is a step of leaving the second insulating film only on the side walls of the opening by anisotropic etching, and after introducing impurities of the second conductivity type into the semiconductor substrate from the opening, polycrystalline silicon or amorphous silicon is added. a step of growing and introducing a first conductivity type impurity and heat treatment; a step of selectively leaving the polycrystalline silicon or amorphous silicon layer in a region above the opening that will become an emitter; 1. A method of manufacturing a semiconductor device, comprising the step of forming an opening to form a base contact, and forming wiring in the emitter and base contact portions.