JPS6329306A - Digital data generating device - Google Patents

Abstract

PURPOSE:To generate digital data by providing a peak position data generating means, a first level comparing means and a second and third level comparing means and controlling a bistable circuit. CONSTITUTION:At the peak level position of an equalizing signal, the first data to invert a polarity are generated, the second data with a different polarity are respectively generated corresponding to the positive and negative areas of the equalizing signal, the frequency component corresponding to the uncertain area is interrupted from the second data, the level of the signal is respectively level-compared with reference levels +Va and -Va, the peak level position of the equalizing signal is identified, synchronized to the polarity inverting time point of the first data, an SR-FF circuit 42 is set and reset and the digital data are generated. namely, the output of level comparing circuits 38 and 39 comes to be the window to control whether or not the first data outputted from a level comparing circuit 33 are guided to the SR-FF circuit 42. For this reason, the correct digital data can be generated without needing to execute the band limit.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) This invention is applicable to magnetic devices such as digital audio chip recorders, etc. 512 digital data generation techniques for converting excellent reproduction signals from magnetic recording media into original digital data, related to digital recording and reproducing systems using recording and reproducing media! Regarding improvement of 2.

(Prior art) As is well known, in the field of audio Wi-Fi devices, information signals such as audio signals are processed by PC~1 (pulse code modulation) in order to achieve high density and high fidelity recording and playback. BACKGROUND ART Digital recording and reproducing systems that convert digital data using technology, record it on a recording medium such as a magnetic tape or a disk, and reproduce the data are now in widespread use.

Among these, those that use magnetic tape as a recording medium are called digital audio chip recorders.
For example, a fixed head type with multiple heads arranged in the width direction of the tape, and a helical scan performed by winding the tape around a cylindrical drum with heads rotating along the circumference. There is also a rotating head type.

Here, FIG. 6 shows a portion related to the recording and reproducing operation of such a digital audio chip recorder.

First, to explain the recording operation, an analog information signal supplied to the input terminal 11 is converted into digital data by an A, /D (analog/digital) conversion circuit 12.

This digital data is subjected to necessary digital signal processing such as parity generation and modulation in the signal processing circuit 13, thereby generating digital data for recording as shown in FIG. 7(a). is supplied to the amplifier 14 for use.

As shown in FIG. 7(b), this recording amplifier B14 generates a recording current of ±I according to the input digital data and outputs it to the recording head 15. is magnetized, and digital data is recorded onto the tape 16 here.

On the other hand, during playback, the digital data recorded on the chip 716 is read by the playback head 17, and as shown in FIG. An electrical reproduction signal having a peak level is obtained.

This reproduced signal is supplied to the data conversion circuit 19 via the amplifier circuit 18 to generate digital data. Then, this digital data is subjected to data identification by a data identification circuit 20 based on a synchronous clock signal extracted by a PLL (phase locked loop) circuit 21, and jitter components are absorbed.

Further, the digital data generated by the data identification circuit 20 is subjected to necessary digital processing such as demodulation and error correction in the signal processing circuit 13, and then processed in the D/A (digital/analog) conversion circuit 22. The signal is converted into the original analog information signal and outputted via the output terminal 23 to an analog reproduction circuit system (not shown), where the digital data recorded on the tape 16 is reproduced.

Here, as shown in FIG. 8, the data conversion circuit 19 is connected to the equalization circuit 24. Integration circuit 25 and level comparison circuit 2
It has been developed since 6. The reproduced signal output from the amplifier circuit 18 is supplied to the equalization circuit 24 via the input terminal 27. Here, as described above, the reproduced signal has the maximum and minimum peak levels at the time of polarity reversal of the digital data, but the magnetization reversal interval on the tape 16 is shorter than the polarity reversal interval of the digital data. Therefore, pulse interference occurs, and as shown in FIG. 7(C), a so-called peak shift PS may occur in which the polarity inversion point of the digital data and the peak position of the reproduced signal are shifted.

The equalization circuit 24 is provided to correct this peak shift PS, and uses, for example, a transversal filter to perform pulse narrowing (by humming, as shown in FIG. 7(d)). An equalized signal without a peak shift PS is generated.Then, this equalized signal is passed to the 0 level line at the peak position of the equalized signal by the integrating circuit 25, as shown in FIG. 7(e). Then, this integrated signal is level-compared with the ground level (O level) in the level comparison circuit 26, so that the output terminal 28 receives a signal as shown in FIG. 7(f). Digital data equivalent to the original digital data is obtained, and digital data is generated here.

By the way, in the digital data generating means as described above, no problem will occur if it is assumed that the recording/reproducing characteristics to the chip 116 are in an ideal state. However, in an actual recording/reproducing system, the tape 16
accurate digital data, such as 1jfi sound and distortion generated in the amplifier circuit 18, dropouts of the playback signal due to defects in the tape 16 itself, instability of the contact state between the Qi 716 and the playback head 17, etc. There are many factors that hinder the generation of

In particular, with the above-mentioned integral type digital data generation means, noise and distortion in the low frequency band,
Factors such as variable vJ cannot be ignored because they have a great negative effect on the generation of digital data.

Specifically, FIG. 9(a) shows the frequency characteristics of a recording/reproducing device using a general magnetic tape. That is, the reproduced signal component A is about 6 dBlo
It has a characteristic that the gain increases in the high frequency direction with the slope of ct, peaks at a specific frequency, and decreases from frequencies above that. In this case, the noise component B exists at a low level over the entire area.

Then, in the data conversion circuit 19, as shown in FIG. 9<b>, the equalization circuit 24 increases the high frequency range of the reproduced signal component A from the state shown by the dotted line in the figure to the state shown by the solid line and narrows the pulse. , by passing through the integrating circuit 25, the reproduced signal component A is made to have flat amplitude characteristics from direct current to high frequencies.

However, if the reproduced signal component A is made to have a flat amplitude characteristic, the noise component B will be emphasized in the same way as the reproduced signal, which will adversely affect the generation of digital data as described above. .

Therefore, as shown in FIG. 9(C), conventional methods have been used to prevent the characteristics of the reproduced signal component A from becoming too flat down to a low frequency band, that is, to prevent the integration circuit 25 from extending its integration effect to a low frequency band. The band is limited to prevent the noise component B from being emphasized.

However, if the band of the integrating circuit 25 is limited too much, the following problem will occur. In other words, Fig. 10 (
When the tape 16 on which digital data as shown in a) is recorded is reproduced, and the equalization circuit 24 obtains an equalized signal as shown in FIG. In the portion where the inversion interval is long, the integration effect is insufficient, and the output of the integration circuit 25 converges to the vicinity of the 0 level, as shown by the solid line in FIG.

Therefore, the digital data obtained by level comparing the integrated signal and the 0 level in the level comparison circuit 26 includes the 10th level.
As shown in Figure (d), an uncertain region F is generated, making it impossible to generate accurate digital data.

(Problems to be Solved by the Invention) As described above, in the conventional digital data generation means, when trying to flatten the frequency characteristics of the reproduced signal using an integrating circuit, the noise component is emphasized, and this fit sound This has a problem in that the generation of digital data is adversely affected by this. In addition, if band limitation is applied to the integrating circuit in an attempt to solve this problem, uncertainties will occur in the digital data in areas where the magnetization reversal interval is good.
Again, a problem arises in that it is impossible to generate positive digital data.

Therefore, this invention has been made in consideration of the above circumstances, and is an extremely good digital data generation program that is less susceptible to noise components and can generate accurate digital data.
The purpose is to provide equipment.

[Structure of the invention] (Means for solving the problem) That is, the digital data generation device according to the present invention has the following features:
peak position data generation means for generating data whose polarity is inverted at approximately the peak position of the level of the reproduced signal; first level comparison means for comparing the level of the reproduction signal with a first reference level; and the first level comparison. filter means for cutting off frequency components corresponding to the uncertain region from the output of the means; and second and third level comparing means for comparing the output signal level of the filter means with second and third reference levels different from each other. and 8, the output of the beak position data generation means and the output of the first and second level comparison means are logically ANDed, and the bistable circuit is constructed based on each logical product output υ1'
60 to generate digital data.

(For FF) According to the above configuration, since the integration method is not used as in the past, there is no need to raise the low frequency components of the reproduced signal to flatten the frequency characteristics, and the noise components are emphasized. You will no longer be exposed to it. Therefore, it is possible to solve the problem that the generation of digital data is adversely affected by noise components. Further, since there is no need to limit the low frequency range, there is no uncertainty region in the generated digital data, and accurate digital data can be generated.

(Tora Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In FIG. 1, 29 is the reproducing head 1.
This is an input terminal to which reproduced signals from 7 to 4 are supplied via the amplifier circuit 18. This input terminal 29 is connected to the equalization circuit 3
0 to the differentiating circuit 31 and to the non-inverting input terminal of the level comparing circuit 32.

The output terminal of the differentiating circuit 31 is connected to a non-inverting input terminal of a level comparing circuit 33. The inverting input terminal of this level comparison circuit 33 is grounded, and its output terminal is connected to one input terminal of a NAND circuit 35 via a NOT circuit 34, and one input terminal of another NAND circuit 36. It is connected to the.

Further, the inverting input terminal 1 of the level comparison circuit 32 is grounded, and its output terminal is connected to the non-inverting input terminal + and the inverting input terminal 1 of the level comparison circuits 38 and 39 via the low-pass filter circuit 37, respectively. It is connected. Further, the inverting input terminals - and non-inverting input terminals + of the level comparison circuits 38 and 39 are connected to voltage terminals 40 and 41 to which reference voltages +Va and -Va are applied, respectively. Further, the output ends of the level comparison circuits 38 and 39 are respectively connected to the other input ends of the NAND circuits 35 and 36.

The output terminals of these NAND circuits 35 and 36 are connected to the set input terminal S and reset input iR of a set-reset flip-flop circuit (hereinafter referred to as 5R-FF circuit) 42.
It is connected to the. Further, the output terminal Q of this 5R-FF circuit 42 is connected to the data identification circuit 20 and the PLL circuit 21 via an output terminal 43.

The operation of the above configuration will be described below with reference to the timing diagram shown in FIG.

Note that the waveforms shown in Fig. 2 (1) to (k) are the first waveforms.
Signals at points (b) to (k) in the figure are shown.

First, assuming that digital data as shown in FIG. 2<a) is recorded on a magnetic tape (not shown), the equalization circuit 30 outputs the positive inversion of the digital data as shown in FIG. 2(b). An equalized signal having a peak level at the instant is generated. This equalized signal (, t) is supplied to the differentiating circuit 31, and as shown in FIG. 2(C), a differentiated signal having a 0 level at its peak level position is generated.

Then, the level comparison circuit 33 compares the level of the differential signal with the ground level (O level).
From the level comparison circuit 33, as shown in FIG.
Synchronized with the above digital data (the first one where the aqueous color is reversed)
data is generated.

In this poultry house and the above first data, there is an uncertain region 1F in a section where the magnetization reversal interval is good.

Further, as the level comparison circuit 32 compares the level of the equalized signal with the ground level (O level), the level comparison circuit 32 outputs the following signal as shown in FIG. 2(e).
Second data having an H level and a low level is generated corresponding to the positive and negative regions of the equalized signal. And this second
Also in the data, an uncertain region F exists in a section where the magnetization reversal interval is long, that is, in the same section as the first data.

Then, this second data is transmitted to the low-pass filter circuit 3.
7, and after the frequency components in the uncertain region are cut off, as shown in FIG. 2<f), the level comparator circuit 38.
39, the reference level +Va.

-Va and the respective levels are compared. Therefore, from each level comparison circuit 38, 39, Fig. 2 mg),
A signal as shown in <h) is now generated.

Thereafter, the output of the level comparison circuit N38 and the signal obtained by inverting the output of the level comparison circuit 33 by the NOT circuit 34 are supplied to the NAND circuit 35, so that the output from the NAND circuit 35 is as shown in FIG. A signal as shown is generated. In addition, the outputs of the level comparison circuits 33 and 39 are output from the NAND circuit 3
6, the NAND circuit 36 generates a signal as shown in FIG. 2(j).

Then, when the output of the NAND circuit 35 falls, the 5R-FF circuit 42 is set, and when the output of the NAND circuit 36 falls, the 5R-FF circuit 42 is reset.
- From the output terminal Q of the FF circuit 42, as shown in FIG. 2(k), the same digital data as the digital data shown in FIG. It is done.

Therefore, according to the configuration of the above embodiment, first data that is positively inverted at the peak level position of the equalized signal is generated. Further, second data having different yields are generated corresponding to the positive and negative regions of the equalized signal, and frequency components corresponding to the uncertain regions are cut off from this second data,
The level of the signal is compared with reference levels +va and -va to identify the peak level position of the equalized signal. Then, with the peak level position identified, the first data (5R
-The FF circuit 42 is set and reset to generate digital data.

That is, the outputs of the level comparison circuits 38 and 39 convert the first data output from the level comparison circuit 33 into 5R-FF.
This is a quind that controls whether or not to lead to the circuit 42.

For this reason, with respect to the frequency characteristics of the reproduced signal component A and Mu component B as shown in FIG. 3(a), the peak level position is detected by a means that does not emphasize the low frequency components. As shown in (b), the low-frequency noise component B is not emphasized.

Furthermore, accurate digital data can be generated without the need for band limitation.

However, if the differential effect is extended to high 1, noise components in the 9th range may become a problem, so see Figure 3 (C).
As shown in Figure 2, even if the differential effect is not extended to high frequencies and the band is limited so that the characteristic shown by the dotted line in the figure changes to the characteristic shown by the solid line, an increase in noise in the high range is prevented. It's good.

Next, FIG. 4 shows a modification of the above embodiment, and shows means for generating the first data without using the above-mentioned differentiation circuit 31. That is, the equalized signal is directly supplied to the non-inverting input terminal of the level comparison circuit 33, and is also supplied to the inverting input terminal of the level comparison circuit 33 via the delay circuit 44.

According to such a configuration, when digital data as shown in FIG. is generated, and from the delay circuit 44, the oil 11b in FIG.
An equalized signal shown by can now be obtained. Therefore, by comparing the levels of the equalized signals shown by curves a and b, first data as shown in FIG. 5<C) is generated.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] Therefore, as detailed above, according to the present invention, it is possible to provide an extremely good digital data generation device that is less susceptible to the effects of noise components and can generate accurate digital data. .

[Brief explanation of the drawing]

Fig. 1 is a block configuration diagram showing an example of a digital data generation machine according to the present invention, Fig. 2 is a timing diagram for explaining the operation of the embodiment, and Fig. 3 is a diagram of the embodiment. FIGS. 4 and 5 are characteristic curve diagrams for explaining the effects, respectively. FIGS. 4 and 5 are block configuration diagrams showing a modification of the same embodiment and timing diagrams for explaining its operation. FIG. 8 is a block configuration diagram showing parts related to recording and dual-playback operations of a digital audio chip recorder and a timing diagram for explaining the operations. FIG. 8 is a block configuration diagram showing a conventional digital data generation means.
Figure 0 is a characteristic curve diagram and a timing diagram, respectively, for explaining the problems of the conventional digital data generation means. 11... Input terminal, 12... A/D conversion circuit, 13
... Signal processing circuit, 14... Recording amplifier, 15.
... Recording head, 16... Tape, 17... Playback head, 18... Amplifying circuit, 19... Data conversion circuit, 20... Data identification circuit, 21... PLL circuit,
22... D/A conversion circuit, 23... Output terminal, 24
... Equalization circuit, 25 ... Integration circuit, 26 ... Level comparison circuit, 27 ... Input terminal, 28 ... Output terminal, two ... Input terminal, 30 ... Equalization Circuit, 31...
・Differential circuit, 32.33... Level comparison circuit, 34・
...Knot circuit, 35.36...Nand circuit, 37.
...Low pass filter circuit, 38.39...Level comparison circuit, 40.41...Voltage terminal, 42...5R-
FF circuit, 43...output terminal, 44...delay circuit. Applicant's agent Patent attorney Takehiko Suzue (a),,,j Figure 2 f (Hz) <c> (a) Figure 8 (c) f (H2)

Claims (1)

[Claims] In a digital data generation device that reproduces a recording medium on which digital data is recorded and generates original digital data from the reproduced signal, peak position data generation generates data whose polarity is inverted at approximately the peak position of the level of the reproduced signal. means, first level comparison means for comparing the level of the reproduced signal with a first reference level, filter means for cutting off frequency components corresponding to the uncertainty region from the output of the first level comparison means; second and third level comparing means for comparing the output signal level of the filter means with second and third reference levels different from each other; and comparing the output of the peak position data generating means and the first and second levels. 1. A digital data generation device comprising: data generation means for generating the digital data by performing logical products with the outputs of the means and controlling a bistable circuit based on the respective logical product outputs.