JPS63292681A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To shorten a time required for an annealing step, by constituting a bulk device and an SOI device in a mixed pattern on the same substrate, determining the arranging direction of a transistor, which is formed in an annealed region, constituting the transistor having less leaking currents, and performing selective annealings, which are divided into two directions. CONSTITUTION:A bulk region C and annealed region A are formed on the same semiconductor substrate. A bulk device is provided in the part of the bulk region C. An SOI device is provided at the part of the annealed region A. At this time, the annealed region A is formed by annealing, which is performed by scanning a laser beam in the parallel direction with the side of the bulk region C. When a transistor is formed on this chip 6, the direction of S/D (connecting direction of a source S and a drain D) becomes the vertical direction and the direction of a gate G becomes the horizontal direction in the region A. In the region B, the direction of S/D becomes the lateral horizontal direction, and the direction of the gate G becomes the vertical direction. Thus a crystal grain boundary becomes vertical with respect to the direction of S/D, and the increase in leaking currents is prevented.

Description

[Detailed Description of the Invention] [Summary] We propose a semiconductor device in which a bulk device and an SOI device are mixed on the same chip, and also describe the scan direction during annealing in the annealing region that forms the SOI device, and the The arrangement direction of the transistors to be formed is defined.

We also propose a manufacturing method, particularly an annealing method in the SOI device region.

[Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly relates to a semiconductor device and a method for manufacturing the same.
OI (Silicon On In5ulato)
r) It relates to a semiconductor device in which devices and bulk devices coexist, and a method for manufacturing the same.

[Conventional technology]

When manufacturing semiconductor devices (hereinafter referred to as devices), unlike the conventional method of forming various elements on the bulk surface of a silicon wafer, an insulating film is formed using SiO2 or the like on the silicon wafer, and then polysilicon is deposited. There is an SOI method in which various elements are formed in this portion after melting and recrystallizing it by an annealing method such as laser annealing or electron beam annealing.

BACKGROUND ART Bulk device manufacturing methods have been widely used for manufacturing various semiconductor devices, and a wide variety of device manufacturing methods are already known.

On the other hand, since a device formed by SOI is formed on a thick insulating film, there is no interaction with other parts, and an element with an ideal structure can be formed. It is particularly suitable for high-voltage devices and is advantageous for manufacturing high-speed devices, and has the advantage of simplifying the manufacturing process for CMO3 devices in which N-channel transistors and P-channel transistors are formed at the same time. Furthermore, since it is formed on an insulating crotch, it is easy to separate the elements.

[Problem that the invention seeks to solve]

Conventionally, the method for manufacturing bulk devices and the method for manufacturing SOI devices are completely separate, and no attempt has been made to realize a device in which both of these devices are mixed.

However, by combining the features of both bulk devices and SOI devices, it is possible to construct a semiconductor device that is suitable for a wider range of uses. The present invention combines bulk devices and SOI on one chip.
In this paper, we propose a new device in which bulk devices such as logic elements are formed at the center of the chip, and SOI devices such as output elements are formed at the periphery. It is advantageous in terms of element arrangement to use a formed structure.

In this case, if annealing is selectively performed on the periphery of a large number of chips on a wafer, there is a problem in that the manufacturing time will inevitably be significantly increased. The purpose of the present invention is to provide a method that can solve these problems and form SOI devices only in the periphery in a short period of time.

[Means for solving problems]

In order to solve the problems of the prior art, the semiconductor device of the present invention has a bulk region 2 on the same semiconductor substrate 1 and a structure orthogonal to the bulk region, as shown in FIG. An annealing region 3 is formed in a portion touching at least two sides of the substrate, a bulk device is provided in the bulk region 2 portion, and an SOI device is provided in the annealing region 3 portion. In this case, the annealed region 3 is formed by annealing by scanning in a direction parallel to the side of the bulk region 2 that the annealed region contacts. Further, the transistors in the SOI device provided in the annealing region 3 are arranged so that the S/D direction thereof is perpendicular to the scan direction during annealing of the annealing region.

Further, in the semiconductor device manufacturing method of the present invention, when forming a bulk device and an SOI device on the same wafer, band-shaped insulating layers are discretely provided on the wafer in the first and second directions orthogonal to each other. Thereafter, polysilicon is deposited on the wafer, and a first annealing process selectively anneals the wafer by scanning in a first direction along the insulating layer in a first direction to form a first band-shaped annealed region. -IJ is formed on the insulating layer, and in a second annealing step, the wafer is selectively annealed by scanning in a second direction along the insulating layer in a second direction to insulate a second band-shaped annealed region. ≠ formed on the layer, then a bulk device is formed in the region not annealed by the first and second annealing steps, and an SOI device is formed in the annealed region adjacent to the bulk device region.

[For production]

In the semiconductor device of the present invention, as shown in FIG. 1, a bulk region 2 is provided on a chip 7, and annealing regions 3 are provided above, below, and to the left and right of the periphery of the bulk region 2. The bulk region 2 is provided with a bulk device, and the annealing region 3 is provided with an SOI device.

FIG. 2 illustrates selective annealing of chips in the present invention. In the same figure, fal indicates lateral annealing, and the annealing regions 8 above and below the bulk region 7 of the chip 6 are SOI device parts formed by lateral annealing, as shown by the arrows in the figure. It is formed by annealing by repeatedly scanning a laser beam in alternate directions.

(b) shows vertical annealing, and the left and right annealing regions 9 around the hollow region 7 in the chip 6 are SOI device parts formed by the vertical annealing, as shown by the arrows. It is formed by annealing by repeatedly scanning a laser beam alternately in the longitudinal direction. By performing laser beam scanning in two directions in this manner, an annealed region is formed around the bulk region 7 at the center.

In this case, the direction of recrystallized grain boundaries in the annealing region is
Occurs parallel to the scanning direction of the laser beam. The four corners of the chip 6 are each double-annealed, causing recrystallized grain boundaries in the direction scanned later and deteriorating the characteristics, but since the area is small, it is sufficient to avoid these parts when forming the element, and in practice There is no particular problem.

〔Example〕

FIG. 3 (al, (bl) shows a cross-sectional view of an embodiment of the present invention.

(a) For example, a silicon substrate 2 with crystal orientation (100)
1, a thick insulating film 22 made of silicon dioxide (Si02) is provided in the area where the SOI device is to be formed, a thin insulating film 23 is provided in the area where the bulk device is to be formed, and a polysilicon layer 24 is further formed over the entire surface. accumulate. In this case, it is preferable that the insulating film 22 has a thickness of about 1 μm and the polysilicon layer 23 has a thickness of about 0.4 μm.

(b) Next, after recrystallizing the polysilicon 24 on the insulating film 22 by annealing it with a laser beam or the like,
By removing polysilicon other than the annealed region, an annealed region 25 and a bulk region 26 are formed.

FIG. 4 shows an annealing method according to an embodiment of the present invention, in which facet lines 12 are formed on a wafer 11.
Areas parallel to 13 + , 132 , 133 .

134, --- and vertical regions 141, 142.
143.14. , - After forming a thick insulating film 22 on the lower part of the wafer 11, polysilicon is deposited on the entire surface of the wafer 11 by CVD, selective annealing is performed by scanning a laser beam in a direction parallel to the facet line 12, and lateral annealing is performed. Area 13, 132.133.132. −
Then, the wafer 11 is rotated 90 degrees and selective annealing is performed by scanning the laser beam in a direction perpendicular to the facet line 12 to form a longitudinal annealing region 14 +
, 142 , 143 , 144, - are formed. The scanning of the beam may be performed by moving the laser beam or by moving the stage on which the wafer is placed. Further, the annealing method is not limited to a laser beam, and any other annealing method may be used. The annealing regions are arranged in pairs, excluding both ends, with a wide spaced part and a narrow space.

For each bulk region on the wafer formed in this way and the annealing region surrounding it, the annealing region is
Elements are formed with the bulk region as a part of an I device and the bulk region as a part of a bulk device.

Thereafter, horizontal scribe lines 151 , 152 , 153 , - are provided in the center of the narrowly spaced parts of the annealing region in a direction parallel to the facet line 12 , and vertical scribe lines 16 .
．． 162,163. - may be provided and the respective portions may be separated, and the scribe line may be provided in the center by annealing including the scribe line portion of the bulk deformed in the center.

In addition, the annealing regions are not limited to the case where the annealing regions are provided in pairs as shown in FIG. 4, and the annealing regions are provided on the four sides of the bulk region. An annealing region may be provided so as to be in contact with.

FIG. 5 illustrates the direction in which transistors are formed on a chip formed by the method of the present invention. In the same figure, (al) indicates the direction of recrystallized grain boundaries in the annealing region, and since the part A in 1000 Tsubu 6 was annealed by scanning in the horizontal direction as shown by the arrow, the recrystallized grain boundaries are The recrystallized grain boundaries are generated in the horizontal direction, and recrystallized grain boundaries are generated in the vertical direction in the part B because the annealing is performed by scanning in the vertical direction as shown by the arrow.

When forming a transistor on such a chip, in the area A, the S/D
The direction (direction connecting source S and drain D) is vertical, and the direction of gate G is horizontal, and in region B, the S/D direction is horizontal as shown in fc). so that the direction of the gate G is vertical. As is well known, when the S/D direction coincides with the direction of grain boundaries, the leakage current between the source and drain increases because diffusion occurs along the grain boundaries.
If the transistor is oriented as shown in the figure, the crystal grain boundaries will be perpendicular to the S/D direction, thereby preventing an increase in leakage current.

Therefore, when forming an SOI device using the method of the present invention, a mask is created so that the direction of the channel of the transistor is changed by 90 degrees between the part A and the part B in Fig. 3 fa). , (If the transistors are arranged as shown in C1, the orientation of the grain boundaries and S
It is always perpendicular to the /D direction, and leakage current of the transistor can be prevented.

Note that although the crystal orientation during recrystallization in the annealing region is undefined, this does not pose a particular problem in forming a transistor.

FIG. 6 is a sectional view showing an example of the structure of a semiconductor device according to the present invention.

On the silicon substrate 21 on which the annealing region 25 and the bulk region 26 have been formed by the process shown in FIG.
The element is formed by applying OI device manufacturing technology and bulk device manufacturing technology.

In FIG. 6, n+ regions 281 and 282, which become sources and drains, are formed in the annealed region 25 with a p- region 27, which becomes a channel, and a p- region 2.
While forming transistors 31 and 32 consisting of a gate electrode 30 formed on 7 with an insulating film 29 interposed therebetween,
N1 regions 341 and 342 that become sources and drains are formed in the bulk region 26 with a p- region 33 that becomes a channel interposed therebetween, and a gate electrode portion 35 that is formed on the p- region 33 with an insulating film 23 interposed therebetween. It is shown that a transistor 36 consisting of

FIG. 7 is a cross-sectional view showing another example of the configuration of a transistor formed in the SOI device region in the present invention.

In the same figure, the same parts as the transistor shown in FIG.
The P- region 27 is an offset region formed between the + region 282 and is continuous with the n- region 38 formed on the gate electrode side and the region 27 formed on the insulating film 22 side.
．． It consists of

In such a structure, the n+ region 28 which becomes the source
When a voltage is applied between the .degree. At this time, since the lower surface of the 1-transistor is separated from other parts by the insulating film 22, breakdown will not occur between it and other parts. , the pressure resistance performance can be increased arbitrarily.

However, even if a similar structure is created in the bulk device region, since there is no insulating layer underneath, breakdown cannot occur through the silicon substrate and the breakdown voltage cannot be increased.

As an embodiment of the present invention, an example of an annealing method in an annealing region is shown in FIG.
μm, and when the thickness of the polysilicon layer 24 is about 0° to 4 μm, use a continuous wave argon laser (CW-Ar laser) and reduce the laser power to LOW while heating the substrate at 500°C.
Therefore, it is preferable to anneal at a speed of about 150 cm/sec. However, the thickness of the polysilicon layer and the underlying insulating film are arbitrary.

The SOI device area does not need to surround the four sides of the bulk device area, and may be just two or three sides that intersect, but when the number of SOI elements to be integrated is large, it is naturally necessary to widen the SOI device area.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, by configuring bulk devices and S○■ devices in a mixed manner on the same substrate, it is possible to realize a semiconductor device that combines the features of both devices. . Further, at this time, by determining the arrangement direction of the transistor formed in the annealing region, a transistor with low leakage current can be constructed. Further, according to the manufacturing method of the present invention, the time required for the annealing process can be shortened by performing selective annealing in two directions.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention, FIG. 2 is a diagram explaining selective annealing in the present invention, FIG. 3 is a sectional view showing an embodiment of the present invention, and FIG. FIG. 5 is a diagram illustrating the direction in which transistors are formed on a chip; FIG. 6 is a sectional view showing an example of a semiconductor device according to the present invention; FIG. 7 is an SOI FIG. 7 is a cross-sectional view showing another example of a transistor formed in a region. Semiconductor substrate 2: Bulk region 3 Near annealing region 6: Chip 7: Bulk region 8.9 Near annealing region 11: Wafer 12: Facet line 13 Violet, 132, 133, 134, -: Lateral annealing region 14 I, 142 , 143, 144, -: Vertical annealing region 15 I, 152, 153, -: Horizontal scribe line 16 I, 162, 163, -'-: Vertical scribe line 17 +, 172, --- :Bulk area 21:
Silicon substrate 22, 23.29: Insulating film 27, 27+, 33: P- region 28+, 282, 341, 342: n+
Region 3o, ss: Gate electrode 31, 32.367 Transistor 37: Offset region 1 day 38: n- region

Claims (4)

[Claims] (1) A bulk region and an annealing region formed on an insulating layer in contact with at least two orthogonal sides of the bulk region are provided on the same semiconductor substrate, and a bulk device is provided in the bulk region. , SO in the annealing region
A semiconductor device characterized by being provided with an I device. (2) The semiconductor device according to claim 1, wherein the annealing region is annealed by scanning in a direction parallel to a side of the bulk region in contact with the annealing region. (3) The semiconductor device according to claim 2, wherein the transistor in the SOI device is arranged with its source/drain direction perpendicular to the scanning direction during annealing of the region. (4) A method for forming a bulk device and an SOI device on the same wafer, which includes the step of discretely providing strip-shaped insulating layers in the first and second directions perpendicular to the wafer, and the step of forming a polygon layer on the wafer. a step of depositing silicon; and a first annealing step of selectively annealing the wafer by scanning the insulating layer in a first direction along the insulating layer to form a first band-shaped annealed region on the insulating layer. a second annealing step of selectively annealing the wafer by scanning in a second direction along the insulating layer to form a second band-shaped annealed region on the insulating layer; A semiconductor device comprising the steps of: forming a bulk device in a region not annealed in the first and second annealing steps; and forming an SOI device in an annealed region in contact with the bulk device region. Production method.