JPS63289961A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63289961A JPS63289961A JP62125402A JP12540287A JPS63289961A JP S63289961 A JPS63289961 A JP S63289961A JP 62125402 A JP62125402 A JP 62125402A JP 12540287 A JP12540287 A JP 12540287A JP S63289961 A JPS63289961 A JP S63289961A
- Authority
- JP
- Japan
- Prior art keywords
- gate film
- logic circuit
- grow
- gate
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 238000000034 method Methods 0.000 claims abstract description 15
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 3
- 238000002955 isolation Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000010410 layer Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置の製造方法、特にＮＩＯ３型トラ
ンジスタで構成され、高耐圧素子を内蔵させ、電源電圧
が少な（とも２種類以上ある、いわゆる高耐圧半導体装
はの製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, which is composed of an NIO3 type transistor, has a built-in high voltage element, and has a small power supply voltage (both of which are of two or more types). The present invention relates to a method of manufacturing a so-called high voltage semiconductor device.
本発明は、〜１０Ｓ型トランジスタで構成される半導体
装置の製造方法において、ゲート膜厚を、印力ける電圧
に応じて変える製造方法とすることにより、高耐圧化と
、微細化、及び高速化を両立させたものである。The present invention provides a manufacturing method for a semiconductor device composed of ~10S type transistors, which achieves higher breakdown voltage, smaller size, and higher speed by changing the gate film thickness depending on the applied voltage. It is a combination of both.
従来の、高耐圧半導体装置の製造方法は、通常５Ｖで動
作させる論理回路部と、通常５■以上の高耐圧部分とは
同じゲート膜成長工程で製造していた。In a conventional method for manufacturing a high voltage semiconductor device, a logic circuit section that normally operates at 5V and a high voltage section that normally operates at 5V or higher are manufactured in the same gate film growth process.
しかし、前述の従来技術では、論理回路部と高耐圧部で
ゲート膜厚が同じ膜厚であるため、高耐圧部にかける電
圧を高（しようとするとゲート膜厚が厚（なり、論理回
路部の微細化や高速化が出来な（なる。逆に論理回路部
を微細化し、高速化するためにゲート膜厚を薄くすると
、ゲート電圧を上げられず、高耐圧化が出来なくなると
いう問題点を育する。そこで本発明はこのような問題点
を解決するもので、その目的とする所は、論理回路部を
微細化、及び高速化し、なおかつ高耐圧部についてはよ
り高い電圧を印加出来るような高耐圧半導体装五の製造
方法を提供する所にある。However, in the above-mentioned conventional technology, since the gate film thickness is the same in the logic circuit section and the high withstand voltage section, if you try to apply a high voltage to the high withstand voltage section, the gate film thickness becomes thick. On the other hand, if you make the logic circuit part smaller and make the gate film thinner to increase the speed, you will not be able to increase the gate voltage and you will not be able to achieve high breakdown voltage. The present invention is intended to solve these problems, and its purpose is to miniaturize and speed up the logic circuit section, and to make it possible to apply a higher voltage to the high voltage section. The present invention provides a method for manufacturing a high-voltage semiconductor device.
本発明の半導体装置の製造方法は、半導体表面、全面に
、ゲート膜を成長させた後、論理回路部のゲート膜を除
去し、しかるのちに、論理回路部のゲート膜を成長させ
ると同時に高耐圧部のゲート膜を再成長させることを特
徴とする。In the method for manufacturing a semiconductor device of the present invention, after growing a gate film on the entire surface of the semiconductor, the gate film in the logic circuit portion is removed, and then, at the same time, the gate film in the logic circuit portion is grown. The feature is that the gate film in the voltage-resistant part is regrown.
本発明の上記の製造方法によれば、論理回路部のゲート
膜４については、例えば４００人閣することにより、へ
１０Ｓ型トランジスタのチャンネル長としては、約２ｕ
ｍ程度にでき、十分に微細化が可能であり、また、 速
度的にも高速化が計れる。これに対し、高耐圧部のゲー
ト膜５については伊μば１２００人とすることにより、
ゲート電圧としては、約３０Ｖまで印加出来、高耐圧化
が計れる。そして論理回路部のゲート膜厚と高耐圧部の
ゲート膜厚については、半導体装置の要求により自由に
設定出来るため、より自由度のある半導体装置の設計が
可能となる。According to the above-described manufacturing method of the present invention, the gate film 4 of the logic circuit section is formed by, for example, 400 people, so that the channel length of the 10S type transistor is approximately 2u.
It is possible to achieve sufficient miniaturization, and speed-up can also be achieved. On the other hand, by setting the gate film 5 of the high voltage part to 1200 people,
As for the gate voltage, up to about 30V can be applied, and high breakdown voltage can be achieved. Since the gate film thickness of the logic circuit portion and the gate film thickness of the high breakdown voltage portion can be freely set according to the requirements of the semiconductor device, it is possible to design the semiconductor device with more flexibility.
第１図は本発明の半導体装２′の製造方法の実施例に於
ける工程図である。以下、第１図にしたがうて本発明の
製造方法を説明する。FIG. 1 is a process diagram in an embodiment of the method for manufacturing a semiconductor device 2' of the present invention. The manufacturing method of the present invention will be explained below with reference to FIG.
（第１図（ａ）） １の例えばＳｉ基板に分離領域の
例えば酸化Ｂ２を例えばＬＯＣＯ３法で形成したのち、
全面にゲート膜を、例えば熱酸化法により、酸化膜を例
えば９００人成長させる。(FIG. 1(a)) After forming an isolation region, e.g., oxide B2, on e.g., Si substrate 1 by e.g., LOCO3 method,
A gate film, for example, a 900 oxide film is grown on the entire surface by, for example, a thermal oxidation method.
（第１図（ｂ）） 例えばＡ２１３５０などのレジスト
３を露光法により形成し、論理回路部が形成される部分
のゲート膜を除去する。(FIG. 1(b)) A resist 3 such as A21350 is formed by an exposure method, and a portion of the gate film where a logic circuit portion is to be formed is removed.
（第１図（ｃ）） Ｌかるのちに、論理回路部のゲー
ト膜４を、例えば熱酸化法により、酸化膜を例えば４０
０人成長させる。このときに同時に高耐圧部のゲート膜
５は再成長し、９００人から１２００人に成長している
。(FIG. 1(c)) After the L is completed, the gate film 4 of the logic circuit section is heated to an oxide film of, for example, 40% by thermal oxidation method.
Grow 0 people. At the same time, the gate film 5 of the high breakdown voltage section is regrown, and the number of members has grown from 900 to 1,200.
（第１図（ｄ）） その後、通常の方法でゲート電極６
を例えばポリＳｉで形成し、ＭＯＳ！）う／ジスタのソ
ースとドレインとなる拡散層７を、例えばイオン注入法
で形成する。(Fig. 1(d)) After that, the gate electrode 6 is
is made of poly-Si, for example, and MOS! ) Diffusion layers 7 which become the source and drain of the transistor are formed by, for example, ion implantation.
（第１図（ｅ）） そして、層間絶縁ＷＸ：８として例
えばＰＳＧを、例えば気相成長法で形成し、しかるのち
に配ｔｌＡ電極９として、例えばＡ１を例えばスパッタ
法で形成する。(FIG. 1(e)) Then, as the interlayer insulation WX:8, for example, PSG is formed by, for example, vapor phase growth, and then as the tlA electrode 9, for example, A1 is formed by, for example, sputtering.
以上述べた様に本発明の製造方法によれば、半導体表面
全面にゲート膜を成長させた後、論理回路部のゲート膜
を除去し、しかるのちに論理回路部のゲート膜を成長さ
せる製造方法としたことにより、論理回路部のゲート膜
厚と高耐圧部のゲート膜厚を自由に設定することが出来
、論理回路部の微細化が可能であり、また、速度的にも
高ｄ化か計れ、高耐圧部については高耐圧化が可能にな
ると言う効果を有する。As described above, according to the manufacturing method of the present invention, after growing a gate film on the entire surface of the semiconductor, the gate film in the logic circuit portion is removed, and then the gate film in the logic circuit portion is grown. By doing so, the gate film thickness of the logic circuit part and the gate film thickness of the high breakdown voltage part can be set freely, making it possible to miniaturize the logic circuit part, and also to increase the speed. This has the effect of making it possible to increase the withstand voltage of the high withstand voltage section.
第１図（ａ）〜（ｅ）は、本発明の半導体装置の一実施
例を示す工程図。
１・・・Ｓｉ基板
２・・・分離領域
３・・・レジスト
４・・・論理回路部のゲート膜
５・・・高耐圧部のゲート膜
６・・・ゲート１！極
７・・・拡散層
８・・・ＰＳＧ
９・・・配線電極
以 上FIGS. 1(a) to 1(e) are process diagrams showing one embodiment of the semiconductor device of the present invention. 1...Si substrate 2...Isolation region 3...Resist 4...Gate film 5 of logic circuit section...Gate film 6 of high breakdown voltage section...Gate 1! Pole 7... Diffusion layer 8... PSG 9... Wiring electrode and above
Claims (1)
ート膜を成長する工程と、前記半導体主表面上の一部の
ＭＯＳ型トランジスタのゲート膜を除去する工程と、前
記除去した部分のＭＯＳ型トランジスタのゲート膜を成
長させると同時に、除去しない部分のゲート膜を成長さ
せる工程からなることを特徴とする半導体装置の製造方
法。a step of growing all the gate films of MOS transistors on the main surface of the semiconductor, a step of removing the gate films of some MOS transistors on the main surface of the semiconductor, and a step of growing the gate films of the MOS transistors in the removed portions. A method for manufacturing a semiconductor device, comprising the steps of growing a gate film and simultaneously growing a portion of a gate film that will not be removed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125402A JPS63289961A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62125402A JPS63289961A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63289961A true JPS63289961A (en) | 1988-11-28 |
Family
ID=14909238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62125402A Pending JPS63289961A (en) | 1987-05-22 | 1987-05-22 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63289961A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
| US5359216A (en) * | 1983-02-23 | 1994-10-25 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
-
1987
- 1987-05-22 JP JP62125402A patent/JPS63289961A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5244825A (en) * | 1983-02-23 | 1993-09-14 | Texas Instruments Incorporated | DRAM process with improved poly-to-poly capacitor |
| US5359216A (en) * | 1983-02-23 | 1994-10-25 | Texas Instruments Incorporated | DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
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